Cryogenic Alternative: CMOS Versus Dynamic-Based Logic

Next-generation data-center computing requires high-performance energy-efficient servers. One counterintuitive approach to reduce energy is to lower the temperature of the processing elements even down to cryogenic temperatures of liquid nitrogen. If the processing load is reduced dramatically, the net energy cost is lower even considering the corresponding cooling cost. Operating at such temperatures will require one to utilize optimized devices and new circuit techniques. One technique is scaling down the threshold voltage of transistors which in turn allows the supply voltage to scale. Another technique is to leverage the reduced leakage and to use dynamic-based logic for processing. This paper utilizes a low-temperature low-threshold (LTLVT) model of a 14-nm FinFET device calibrated with measurements for cryogenic computing. A demonstration of a 16-bit NP-CMOS adder is presented for an energy-delay optimization up to 20X at 77K compared to 330K.

I. Introduction

Recently, cryogenic computing has garnered interest as a promising technology for high-performance, energy-efficient data centers. This interest arises from the fact that current technologies are experiencing a slowdown in performance improvement due to the power wall [1], while cryogenic computing offers performance boosters to mitigate this issue. These boosters can be summarized as steeper subthreshold slopes that eliminate leakage current, allowing for scaling down of the power supply, reduced wire resistance for energy-efficient interconnects, and enhanced carrier mobility[2]. Additionally, cryogenic computing can help mitigate thermal challenges at advanced technology nodes[3], [2], [4].