Contents I. Introduction
Advanced system-on-chips (SoCs) comprise a broad variety of modules, such as multi-core processors, memory units, I/O interfaces, power management systems, and wireless transceivers [1]. Each of these systems usually functions within their own dedicated, carefully optimized clock domain with its own crystal reference oscillator and PLL to achieve the desired performance. Moreover, certain applications necessitate extremely low-jitter and high-frequency clocks. Consequently, there arises a requirement for efficient, low-power, and compact methods of generating multiple clock signals of harmonically unrelated frequencies that must exhibit ultralow-jitter and exceptional spectral purity preferably from a single reference oscillator. PLL-based frequency synthesis—whether analog or digital—is capable of achieving exceptionally low jitter and minimal spur levels [2], [3], [4]. However, the constraints of VCO size and power consumption make it impractical to replicate this component for multiple on-chip clock generators [3], [5].
