A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs

This article presents a switched-capacitor (SC) delta–sigma modulator (DSM) for low-power and high-precision applications. With a 5-bit noise-shaping (NS) successive-approximation-register (NSSAR) quantizer embedded in the 2nd-order loop filter, the system achieves a stable 3rd-order noise transfer function (NTF) without coefficient scaling. Partial feedback with digital filters is adopted, which only feeds back the 3 MSBs, leading to a fourfold reduction of data-weighted-averaging (DWA) complexity. To mitigate the noise leakage, a gain-boosted two-stage floating inverter amplifier (FIA) with 87.2-dB open-loop gain is proposed with the assistance of the Correlated-level-shifting (CLS) technique. The stability and noise performance of the FIA are also optimized. Fabricated in a 55-nm CMOS process, the prototype analog-to-digital converter (ADC) achieves a measured 93.7-dB signal to noise and distortion ratio (SNDR) in a 10-kHz bandwidth at 800 kS/s at a oversampling ratio (OSR) of 40. With 33.2- $\mu \text{W}$ power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 178.5 dB and a Walden FoM of 41.9 fJ/conv, demonstrating state-of-the-art energy efficiency. Furthermore, the prototype exhibits fully dynamic characteristics and capabilities to a higher dynamic range (DR).

I. Introduction

Flourishing development of smart sensors and the Internet-of-Things (IoT) applications are strongly expecting high dynamic-range (DR) analog-to-digital converters (ADCs) with micro-power consumptions. Beneficial from oversampling and noise-shaping (NS), switched-capacitor (SC) modulators have already shown outstanding performance in this scenario for their dynamic operation, process robustness, and clock jitter immunity [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11]. Nevertheless, integrators based on power-hungry operational transconductance amplifiers (OTAs) are the bottleneck of power reduction [1], [2], [3], [4], [5], [6], [7]. Noise-shaping (NS) successive-approximation-register (NSSAR) ADCs combine the benefits of delta–sigma modulator (DSM) and SAR, demonstrating excellent power efficiency over a wide range of signal frequencies. However, the mitigation of element mismatch relies on either off-chip foreground calibration or on-chip methods like dynamic element matching (DEM) [12], which improve the linearity at the cost of indispensable digital logic overhead and mismatch error shaping (MES) [13], [14], [15], which is much efficient but requires compensation techniques to maintain the full-scale input range. Zoom ADCs also have gained popularity for the appropriate tradeoff among resolution, power, and design complexity. However, the signal to quantization noise ratio (SQNR) loss caused by the over ranging and the out-of-band interference are knotty issues [5], [6], [7].