Design and Optimization of a Gilbert Cell Down-Conversion Mixer for Improved Linearity, Noise Figure, and Conversion Gain

This paper discusses a design process for a balancing Noise Figure, Conversion Gain, Linearity, and Power Consumption for Gilbert cell mixer topology based on 90 nm CMOS technology utilizing the Voltage Biasing technique. The simulation run on the optimized model shows a conversion gain of 10.034 dB, an input third-order intercept point at 9.68 dBm, a noise figure of 9.51 dB, and a power consumption of 4.2 mW. The designed Gilbert cell mixer is a suitable choice for RF applications that require high conversion gain, low noise figure, low power consumption, and high linearity.

I. Introduction

In recent years, the demand for high-performance and low-power radio frequency (RF) front-end circuits has significantly increased due to the proliferation of wireless communication systems. Mixers play a vital role in RF transceivers as they facilitate the conversion of high-frequency signals to a lower-frequency range, enabling subsequent processing and demodulation. The Gilbert down-conversion mixer is a popular architecture due to its high linearity and simplicity. It utilizes a pair of transistors biased in the subthreshold region to achieve low-power operation. However, achieving optimal performance in terms of linearity, noise figure, and conversion gain remains a challenging task, especially when considering the shrinking feature sizes of CMOS technologies. The proposed voltage biasing technique offers a promising alternative to current bleeding, inductive resonance techniques, and gm/ID based width optimization methods. By leveraging its advantages of improved linearity, reduced noise figure, enhanced conversion gain, simpler implementation, and process compatibility [1]–[2]. CMOS based Gilbert-cell mixers with improved linearity, broadband low power is presented in [3]–[4]. A systematic approach is used to design the mixer for nanoscale technology is proposed in [5]. Double balanced down conversion Gilbert cell mixer using 180nm Technology is designed in [6]–[8]. A SiGe BiCMOS Gilbert down conversion Mixer with high linearity for 5G receiver application is presented in [9]. A low noise mixer in CMOS 65nm technology for K-band application is proposed in [10]. The Gilbert mixer consists of a pair of transistors arranged in a differential configuration. One transistor operates as a switching element, while the other functions as a current source. The switching transistor modulates the input signal, while the current-source transistor provides the necessary biasing and conversion gain. This architecture takes advantage of the non-linear characteristics of the transistors to perform the frequency down-conversion. The switching transistor is typically biased in the subthreshold region, enabling low-power operation and reduced distortion. Its non-linear behavior allows for the mixing of the input RF signal and the local oscillator (LO) signal, resulting in the generation of the desired lower frequency intermediate frequency (IF) signal. The current-source transistor, on the other hand, helps in achieving the desired conversion gain and provides the necessary biasing conditions for optimal performance. In this paper, we present a comprehensive design optimization methodology for a Gilbert down-conversion mixer implemented using Cadence Virtuoso and the technology used is 90nm. The voltage biasing technique provides a more robust and efficient approach compared to traditional current biasing methods, allowing us to exploit the inherent advantages of the CMOS technology.