Loading [MathJax]/extensions/MathZoom.js
PLL-SAR: A New High-Speed Analog to Digital Converter Architecture | IEEE Conference Publication | IEEE Xplore

PLL-SAR: A New High-Speed Analog to Digital Converter Architecture


Abstract:

A novel, high bandwidth Phase-Locked-Loop Successive Approximation Register (PLL-SAR) ADC topology is proposed. To ensure fast loop settling without power hungry TDCs, no...Show More

Abstract:

A novel, high bandwidth Phase-Locked-Loop Successive Approximation Register (PLL-SAR) ADC topology is proposed. To ensure fast loop settling without power hungry TDCs, non-linear settling is exploited. A major advantage of the PLL-SAR is its ability to achieve relatively high resolution without the need for VCO linearity calibration. Simulations of the proposed PLL-SAR ADC in a 22nm FinFET process showed a bandwidth of 13MHz with 1.41mW power consumption for a linearity of 8 bits.
Date of Conference: 06-09 August 2023
Date Added to IEEE Xplore: 31 January 2024
ISBN Information:

ISSN Information:

Conference Location: Tempe, AZ, USA

I. Introduction

As CMOS processes advance, the voltage threshold of the devices shrink more slowly than the supply voltage. In analog-to-digital converters (ADCs), this means that traditional designs that require high gain operational amplifiers are less viable. Moreover, the comparators must deal with reduced voltage headroom and gain, making it more difficult for them to resolve small signals. One approach to avoid these issues is to process signals in the time domain, rather than the voltage domain. Since the speed of circuits increases with smaller process nodes, time-based converters become more viable in smaller technologies with low voltage headroom.

References

References is not available for this document.