I. Introduction
As CMOS processes advance, the voltage threshold of the devices shrink more slowly than the supply voltage. In analog-to-digital converters (ADCs), this means that traditional designs that require high gain operational amplifiers are less viable. Moreover, the comparators must deal with reduced voltage headroom and gain, making it more difficult for them to resolve small signals. One approach to avoid these issues is to process signals in the time domain, rather than the voltage domain. Since the speed of circuits increases with smaller process nodes, time-based converters become more viable in smaller technologies with low voltage headroom.