A novel, high bandwidth Phase-Locked-Loop Successive Approximation Register (PLL-SAR) ADC topology is proposed. To ensure fast loop settling without power hungry TDCs, non-linear settling is exploited. A major advantage of the PLL-SAR is its ability to achieve relatively high resolution without the need for VCO linearity calibration. Simulations of the proposed PLL-SAR ADC in a 22nm FinFET process...Show More
This paper demonstrates a proposed architecture of multi-stage noise-shaping (MASH) structure with noise shaping successive-approximation (NSSAR) ADC. The proposed intrinsic stable 4^{\mathrm{t}\mathrm{h}} order MASH NSSAR ADC can not only take advantage of sharp noise shaping effect but also gain benefits from hardware reuse. With ultra-low oversampling ratio (OSR) the MASH NSSAR is realized in...Show More
In this paper, a fully passive third order continuoustime (CT) $\Delta\Sigma$ Modulator (DSM) is proposed. By utilizing passive filter, the power cheap DSM still faces poor noise shaping. To improve the performance of this fully passive CTDSM, a Sallen-Key (SK) inserted Q enhancement technique is implemented. The inserted novel SK ensures better noise shaping than the fully passive structure. The ...Show More