A 16-Way Low-Loss mm-Wave Power-Dividing Network Using Patch Elements on the SISL Platform | IEEE Journals & Magazine | IEEE Xplore

A 16-Way Low-Loss mm-Wave Power-Dividing Network Using Patch Elements on the SISL Platform


Abstract:

This article proposes a 16-way low-loss millimeter-wave (mm-wave) power-dividing network using patch elements on the substrate integrated suspended line (SISL) platform. ...Show More

Abstract:

This article proposes a 16-way low-loss millimeter-wave (mm-wave) power-dividing network using patch elements on the substrate integrated suspended line (SISL) platform. The power-dividing network consists of a number of the SISL right-angled isosceles triangular patch (RITP) power dividers and SISL patch-based vertical transitions. The main circuit of the SISL RITP power divider is implemented by the RITP with slots. The TM modes of the RITP are adjusted only by adding slots. As a demonstration, an SISL patch-based power divider has been designed in the mm-wave band with a center frequency of 27 GHz and fabricated by the printed circuit board (PCB) process. At 11.1% of the relative bandwidth, the measured insertion loss is less than 0.4 dB and a loss of only 0.3 dB is achieved at center frequency. Moreover, the SISL RITP power divider has been applied in the 16-way mm-wave power-dividing network. A patch-based vertical transition with low loss is also designed for vertical interconnection. The implemented SISL patch-based power-dividing network has the advantage of low loss (less than 2.5 dB within an 8.8% bandwidth) and is highly integrated.
Published in: IEEE Transactions on Microwave Theory and Techniques ( Volume: 72, Issue: 7, July 2024)
Page(s): 4193 - 4209
Date of Publication: 09 January 2024

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I. Introduction

The rapid development of 5G/6G communication technology has led to extensive research on millimeter-wave (mm-wave) phased arrays. In the mm-wave frequency range below 60 GHz, the method of constructing phased arrays using beamforming chips has been widely used [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. The phased array based on this architecture requires a power-dividing network to provide power combination or distribution for all chip units. The power-dividing network is most commonly composed of a cascade of Wilkinson power dividers [1], [2], [4], [5], [6], [7], [10], [12], [13]. However, the current Wilkinson network suffers from two disadvantages: first, the transmission lines used in the Wilkinson power dividers are often in the form of strip lines [2], [4], [6], microstrip lines [6], or coplanar waveguides (CPWs) [5], [10], [12], [13], which result in high transmission loss and generally require an RF driver [8] to compensate for the additional line loss. Second, some designs of the Wilkinson network use the buried resistance process [2], which requires an expensive substrate. Surface mount device (SMD) resistors are usually connected by via holes to avoid the buried resistance process.

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