A 56 GHz InP VCO for Use in 112 GBaud (112 GBit/s NRZ or 224 GBit/s PAM-4) InP Integrated Optical Receiver Front-End CDR Block

This paper presents the design of a 56 GHz voltage-controlled oscillator (VCO) designed in an Indium Phosphide (InP) 0.8 µm kit. InP (III-V) semiconductor technology was chosen since the fastest photodiodes that currently exists on the market (for use with 112 GBaud) make use of InP PIN diodes. The goal is to integrate everything in one die and one technology of InP (including the PIN diode, front-end transimpedance amplifier (TIA), and CDR blocks with the VCO); for this reason InP was used and to assess if such a VCO can be designed for use in 112 GBit/s NRZ (or 224 GBit/s PAM-4) receiving CDR units. The 56 GHz VCO can either be used directly in a half-rate CDR or be used in a full rate 112 GBaud CDR using a frequency doubler circuit. Post-layout electro-magnetic simulations of the VCO had a tuning range of 55 GHz - 58 GHz. The small tuning range is due to the fact that there were no varactors in the InP kit, hence makeshift HBTs with their limited tuning capacitances were used as the core varactors. The VCO used 11.1 mA of current (including periphery circuitry: buffers & current mirrors) from a 3.3 V supply; for a total power consumption of 36.6 mW. The output signal had a phase noise of -98 dBc/Hz at 10 MHz offset (which is comparable to similar InP works). The VCO design used a -gm cross coupled pair that can provide differential oscillation to recover the clock signal from a differential data input. The core size of the VCO (meant to be used as part of a CDR unit) required only 113 µm × 94 µm of layout space.

I. Introduction

As the transmitter speeds for the opto-electrical world becomes faster (for both the electrical front end drivers and lasers), the need for more robust and faster optical receivers is ever arising. Currently the tech industry can now produce 224 GBit/s PAM-4 (112 GBaud) transmitters [1] - [7]. However the receiver world is still lagging behind (in accepting and processing these signals); mainly for three reasons: 1) the receiving photodiodes and their interconnects require a new design paradigm to work at those speeds (since the maximum frequency wavelengths for the required operations are much shorter), 2) typical transimpedance amplifer (TIA) architectures [8] - [11] no longer suffices (i.e. the electronics require out of the box redesign makeup to function at those large bandwidths [12]; which is up to 78.4 GHz for 112 GBaud using Nyquist criterion [13] & [14]), and 3) the signal recovery process is becoming much more complex, where up to 80 tap decision feedback equalizer (DFE) or more (using the help of artificial intelligence) is now being employed to pull the signals out of the noise [15]. As of 2023, instrumentation companies such as Keysight [15] & [16] have demonstrations boasting electrical equipment that can transmit electrical signals of PAM-4 224 GBit/s, however their receivers and BERT (bit error rate test) machines can only measure up to 60 GBaud.