InP HBT XOR and phase-detector for 40 Gbit/s clock and data recovery (CDR)

High-speed XOR and phase-detector circuit necessary for clock and data recovery were designed and fabricated in a self-aligned InP DHBT technology. In the paper, we present the circuit design with the special highlight of the architecture choice and design challenges. Measurements results of fabricated circuits are shown.

I. Introduction

The important increase of communication services, and particularly Internet traffic, requires adequate transmission capability. Terabit/s optical networks [1] are based on a combination of dense wave division multiplexing (DWDM) and high bit-rate (over 40 Gbit/s) per wavelength realized by electrical time division multiplexing (ETDM). The progress in semiconductor technologies allows to realize modules necessary for such high speed operation in a compact way by the integration of different functions such as multiplexing, and resynchronization for the transmitter and clock and data recovery and demultiplexing for the receiver.