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Design Considerations of Time-Interleaved Discrete-Time Beamformers Toward Wideband Communications | IEEE Journals & Magazine | IEEE Xplore

Design Considerations of Time-Interleaved Discrete-Time Beamformers Toward Wideband Communications


Abstract:

Efficient exploitation of wide bandwidth data communication requires antenna array providing high gain across all frequency components for both transmit and receive equip...Show More

Abstract:

Efficient exploitation of wide bandwidth data communication requires antenna array providing high gain across all frequency components for both transmit and receive equipment. In contrast to the frequency-dependent phased array, true-time-delay (TTD) arrays are appealing yet insufficiently investigated alternative for both fast initial access (IA) process and wideband directional data communications. In this brief, the mathematical relationship of delay before and after the frequency conversion is first discussed, which lays a foundation of the TTD beamformed system followed by a step-by- step design procedure and its tradeoff. Finally, system-level analysis is presented to estimate the minimum interleaving factor and silicon area for both IA and data communications associating the circuit design tradeoffs. The three-part analysis aims to provide a quick starter guide to design a TTD array.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 70, Issue: 11, November 2023)
Page(s): 4068 - 4072
Date of Publication: 05 June 2023

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References is not available for this document.

I. Introduction

Wideband beamformed yet energy-efficient solutions are highly desirable for next generation communication system to enable high speed data processing. State-of-the-art beamformed systems are, however, limited in the adoption of phase shifter [1], [2]. This is because that the frequency-dependent response sets a limit on their operational fractional bandwidth. TTD technique has been widely used to replace the phase shifter, striving to achieve beam-squint free data receiving, targeting for wide fractional bandwidth operations. On the other hand, TTD technique can also be applied for beamtraining to achieve low-latency initial access process in the same beamformed system [3]. Compared to most of the existing TTD approaches using passive elements [4], all pass filter [5], and digital approach [6], baseband (BB) TTD using sample-and-hold-circuit [3], [7], [8], [9] has attracted attention owing to its compact and digital friendly nature. Though operation mechanism and measurement results have been demonstrated to prove the efficacy of large delay range and fine resolution in TTD arrays [3], [10], [11], the circuit design considerations and trade-off analysis are insufficiently addressed. Additionally, any circuit functionalities should fit to a specific system needs and always make compromise between performance, and form-factor. However, system-level considerations has merely being quantified and discussed. This brief aims to address these gaps from circuit/component parameter selection for a scalable architecture.

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1.
N. Peng, P. Gu, X. You and D. Zhao, "A Ka-band CMOS 4-beam phased-array receiver with symmetrical beam-distribution network", IEEE Solid-State Circuits Lett., vol. 3, pp. 410-413, 2020.
2.
M. Yaghoobi, M. H. Kashani, M. Yavari and S. Mirabbasi, "A 56-to-66 GHz CMOS low-power phased-array receiver front-end with hybrid phase shifting scheme", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 67, no. 11, pp. 4002-4014, Nov. 2020.
3.
C.-C. Lin et al., "Multi-mode spatial signal processor with rainbow-like fast beam training and Wideband communications using true-time-delay arrays", IEEE J. Solid-State Circuits, vol. 57, no. 11, pp. 3348-3360, Nov. 2022.
4.
M. Li et al., "An 800-ps origami true-time-delay-based CMOS receiver front end for 6.5–9-GHz phased arrays", IEEE Solid-State Circuits Lett., vol. 3, pp. 382-385, 2020.
5.
I. Mondal and N. Krishnapura, "A 2-GHz bandwidth 0.25–1.7 ns true-time-delay element using a variable-order all-pass filter architecture in 0.13 μ m CMOS", IEEE J. Solid-State Circuits, vol. 52, no. 8, pp. 2180-2193, Aug. 2017.
6.
S. Jang, R. Lu, J. Jeong and M. P. Flynn, "A 1-GHz 16-element four-beam true-time-delay digital Beamformer", IEEE J. Solid-State Circuits, vol. 54, no. 5, pp. 1304-1314, May 2019.
7.
E. Ghaderi, A. S. Ramani, A. A. Rahimi, D. Heo, S. Shekhar and S. Gupta, "An integrated discrete-time delay-compensating technique for large-array beamformers", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 66, no. 9, pp. 3296-3306, Sep. 2019.
8.
E. Ghaderi and S. Gupta, "A four-element 500-MHz 40-mW 6-bit ADC-enabled time-domain spatial signal processor", IEEE J. Solid-State Circuits, vol. 56, no. 6, pp. 1784-1794, Jun. 2021.
9.
A. Fikes, P. P. Khial, S. Nooshabadi and A. Hajimiri, "Programmable active mirror: A scalable decentralized router", IEEE Trans. Microw. Theory Techn., vol. 69, no. 3, pp. 1860-1874, Mar. 2021.
10.
V. Boljanovic et al., "Fast beam training with true-time-delay arrays in wideband millimeter-wave systems", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 68, no. 4, pp. 1727-1739, Apr. 2021.
11.
H. Yan, V. Boljanovic and D. Cabric, "Wideband millimeter-wave beam training with true-time-delay array architecture", Proc. 53rd Asilomar Conf. Signals Syst. Comput., pp. 1447-1452, 2019.
12.
M. Soer, "Switched-RC beamforming receivers in advanced CMOS: Theory and design", Nov. 2012.
13.
A. Nagulu et al., "A full-duplex receiver with true-time-delay cancelers based on switched-capacitor-networks operating beyond the delay–bandwidth limit", IEEE J. Solid-State Circuits, vol. 56, no. 5, pp. 1398-1411, May 2021.
14.
A. M. A. Ali et al., "A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration", IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2602-2612, Dec. 2010.
15.
A. M. A. Ali et al., "A 12-b 18-GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration", IEEE J. Solid-State Circuits, vol. 55, no. 12, pp. 3210-3224, Dec. 2020.
16.
Z. Huang et al., "A 6-GHz bandwidth input buffer based on AC-coupled flipped source follower for 12-bit 8-GS/s ADC in 28-nm CMOS", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 69, no. 10, pp. 4163-4167, Oct. 2022.
17.
M. Straayer et al., "27.5 a 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth", Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 464-465, 2016.
18.
S. Kundu et al., "A 1.2 V 2.64 GS/s 8 bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 62, no. 8, pp. 1929-1939, Aug. 2015.
19.
Q. Xu et al., "A switching-less true-time-delay-based beam probing approach for ultra-low latency wireless communications: System analysis and demonstration", IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 69, no. 10, pp. 4113-4117, Oct. 2022.
20.
A. Wadaskar, V. Boljanovic, H. Yan and D. Cabric, "3D rainbow beam design for fast beam training with true-time-delay arrays in wideband millimeter-wave systems", Proc. 55th Asilomar Conf. Signals Syst. Comput., pp. 85-92, 2021.
21.
S. Wu et al., "A 16nm FinFET CMOS technology for mobile SoC and computing applications", Proc. IEEE Int. Electron Devices Meeting, pp. 9.1.1-9.1.4, 2013.
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References

References is not available for this document.