A 56-to-66 GHz CMOS Low-Power Phased-Array Receiver Front-End With Hybrid Phase Shifting Scheme

This paper presents a millimeter-wave phased-array receiver front-end with compact size and low-power consumption. A combination of local oscillator (LO) and radio frequency (RF) phase-shifting schemes is used to reduce the power consumption and RF path loss. Moreover, in the implementation of active circuits, a bulk isolation technique is used to achieve a higher power gain with a minimum number of stages. This technique is also utilized in the RF path phase shifter switches to mitigate the loss. To validate the proposed architecture, a single-element 56-to-66 GHz phased-array receiver front-end is fabricated in a 65-nm bulk CMOS process. Based on the measurement results, the receiver achieves a power gain of ~14.85 dB and a minimum noise figure (NF) of 5.7 dB. The measured average RMS phase and gain errors are ~3.5° and ~0.45 dB, respectively. The input 1-dB compression point (P_-1dB) of the receiver chain is about -19 dBm. The complete receiver, including active balun and required buffers (excluding the LO), consumes ~50 mW from a 1-V power supply and excluding the pads occupies a silicon area of 0.93 mm².

I. Introduction

The demand for high data rate in wireless communication and high-volume data applications such as high-definition video streaming, wireless local area networks (WLANs) and wireless personal area networks (WPANs) has been on the rise. The wide available global spectrum in the unlicensed 60 GHz band is very promising for such applications [1], [2].