An Energy Efficient Architecture of Configurable Logic Block Using Pass Transistor for FPGA

Configurable logic block (CLB) is the fundamental unit of Field Programmable Gate Array (FPGA) technology. This paper aims to design a CLB using pass transistor logic (PTL). The implemented Boolean function is F=A.(B+C). The number of inputs in our proposed CLB can be increased as per the requirement. The design consists of a 3:1 LUT (Look Up Table), D flip-flop and multiplexers. Cadence Virtuoso has been used for design and simulation purpose. The design has been executed using 45 nm process technology and the functionality of each of the units has been tested. Various performance parameters such as active energy, leakage energy, maximum operating frequency etc. have been measured to be 6.205 fJ,1.109 fJ and 50 MHz. The minimum propagation delay (238.8 ps) and the maximum power efficiency (0.31025 nW) have been obtained by Virtuoso Wave calculator. Finally, the optimized physical layout is obtained, which renders minimum area of 797.385 µm², resulting in highly compact integration of transistors.

I. Introduction

FPGA is an integrated circuit that is used to design circuits of high complexity. Owing to low cost, circuit confidentiality and performance improvement FPGAs are being widely used in various sectors such as wired and wireless telecommu-nications, image and signal processing, medical equipment, automotive, robotics, space and aircraft embedded control systems etc [1]. The main component in FPGA embedded systems is CLB. It is used to serve various purposes like executing complex logic functions, memory functions, synchronization etc. in FPGA technology [12]. In the past two decades, extensive research has been performed on both synchronous and asynchronous FPGA systems. In [2], the authors proposed a system that supported both synchronous and asynchronous circuits. The authors in paper [3] designed an algorithm for converting clocked systems to phased logic systems,which had the properties of both synchronous and asynchronous elements. In [9], an asynchronous FPGA is developed where the timing cells replace the global clock. Programmable phased logic cells are used to make a different types of phased logic cells in [10] and [11]. Indira et al. [4] designed a CLB using asynchronous static NULL Convention Logic (NCL) Library. For simulating their design 1.8V, 180nm TSMC CMOS process was used and the whole CLB had a power dissipation of 9.1719 × 10–⁶ Watts.But the state of the art process technology has been shrinked and all the chips and integrated circuits including FPGA block are becoming more and more compact. So, in the current era of nano-structured devices, the CLB proposed in [4] will not be compatible with the state of the art technology and may undergo performance degradation. Fig. 1:

Diagram of configurable logic block (from [14])