An Energy Efficient Architecture of Configurable Logic Block Using Pass Transistor for FPGA

Configurable logic block (CLB) is the fundamental unit of Field Programmable Gate Array (FPGA) technology. This paper aims to design a CLB using pass transistor logic (PTL). The implemented Boolean function is F=A.(B+C). The number of inputs in our proposed CLB can be increased as per the requirement. The design consists of a 3:1 LUT (Look Up Table), D flip-flop and multiplexers. Cadence Virtuoso has been used for design and simulation purpose. The design has been executed using 45 nm process technology and the functionality of each of the units has been tested. Various performance parameters such as active energy, leakage energy, maximum operating frequency etc. have been measured to be 6.205 fJ,1.109 fJ and 50 MHz. The minimum propagation delay (238.8 ps) and the maximum power efficiency (0.31025 nW) have been obtained by Virtuoso Wave calculator. Finally, the optimized physical layout is obtained, which renders minimum area of 797.385 µm², resulting in highly compact integration of transistors.