Modeling and Suppression of Zero-Sequence Circulating Current Resonance for Parallel Interleaved Inverters With Bypass Capacitor-Based Leakage Current Mitigation

Connection of the neutral point of the ac capacitor to the midpoint or positive (negative) rail of the dc link is a cost-effective method to suppress the leakage current to the ground. However, applying it to a modular parallel interleaved inverter system with the common ac and dc bus will induce a zero-sequence circulating current (ZSCC) resonance issue. This article first establishes the common mode equivalent circuit model of the multiparallel inverters system. Second, the generation mechanism of ZSCC resonance is investigated based on the installed impedance model. To guarantee stable operation, the resonance suppression method which combines the sampling instant shift and phase lag compensation is proposed. The frequency aliasing phenomenon and resultant ZSCC dc offset issue due to the sampling instant shift are further analyzed, and an effective suppression scheme of the ZSCC dc offset is proposed by adding an additional ZSCC dc offset control loop. Finally, the comparative experiments verify the effectiveness of the proposed method.

I. Introduction

With the global energy shortage and environmental pollution, more attention has been paid to renewable energy power generation systems such as photovoltaic (PV) system and wind turbine system. As an interface between renewable energy and the power grid, the grid-connected inverter plays an important role in the generation system [1], [2]. However, due to the presence of the PV-to-ground parasitic capacitance, as shown in Fig. 1, it will result in the leakage current issue under the excitation of high frequency (HF) common-mode voltage (CMV) [3]. Excessive leakage current will increase system losses, bring in electromagnetic interference and even threaten personal safety. Based on the standard of DIN VDE 0126-1-1, the peak value of leakage current must be restricted under 300 mA when the PV inverter is connected to the grid [4]. To meet the above restriction, some leakage current suppression methods have been proposed. Based on the existing works of literature, reducing the leakage current can be realized either from software [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], or hardware approaches [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28]. Fig. 1.

Three-phase voltage source converters and their leakage current path.