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Fan Li - IEEE Xplore Author Profile

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This paper presents a complete SystemC-based Wireless Sensor Network model. It implements the entire IEEE 802.15.4 standard, and permits to simulate scenarios at high level, taking hardware and software low level parameters into account, also enabling design space exploration for system level designers.Show More
In this paper, we present the design, fabrication, and characterization of a highly integrated optical 4\,\times\, 4 crossbar based on microring resonator add-drop filters. The designed crossbar structure, as small as 50\,\mu{\hbox {m}}\times50\,\mu{\hbox {m}}, has been fabricated in CMOS compatible silicon on insulator technology. Finally, experimental results proving the proper operation of...Show More
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbon nanotube field-effect transistors (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Through simulations using available models, these gates are shown to operate at 4 GHz. We subsequently compa...Show More
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbon nanotube field-effect transistors (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Through simulations using available models, these gates and a 10-function ALU offering fine-grain reconfigur...Show More
MPSoC interconnect architectures require new design evolution to absorb the high data rate of the future processor evolutions and to absorb the complex data flow of the next application generations. This paper details an interconnect architectural exploration in an MPSoC environment using a multimedia application: a medical imaging. This exploration take into account two opposite interconnect tech...Show More
This paper describes a family of novel dynamically reconfigurable logic gates with double-gate carbon nanotube field-effect transistors (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Through simulations using available models, these gates and a 10-function ALU offering fine-grain reconfigur...Show More
This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-...Show More
The optical clock distribution has been considered to alleviate limitations due to metallic interconnections for future generation of VLSI. It can be interesting only, if it is able to provide some substantial improvement of IC features. This paper studies the effects of the VLSI structure thermal gradients on the clock skew in optical clock distribution network CDN.Show More
Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthe...Show More
This paper describes a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a double-gate carbon nanotube field effect transistor (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Using available models, CNT-DR8F is proposed, simulated and analyzed at 20 GHz operation. We also ...Show More
An ASIC for an integrated microfluxgate sensor uses pulsed excitation, a 2nd-order DeltaSigma modulator, an LPF and an FIR DAC current generator in a fully-digital field-canceling loop to achieve high linearity over a 120muT DR. A low noise floor of 5nTA/radicHz is measured over a 100Hz BW. This ASIC can be adapted to numerous applications since it is fully programmable. The 9mm2 ASIC consumes 36m...Show More
In the near future, multi-processor systems-on-chip (MPSoC) will become the main thrust driving the evolution of integrated circuits. MPSoCs introduce new challenges, mainly due to growing communication through their interconnect structure. Current electrical interconnects face hard challenges to overcome such data flows. Integrated optical interconnect is a potential technological improvement to ...Show More
This paper describes a dynamically reconfigurable 8-function logic gate (CNT-DR8F) based on a double-gate carbon nanotube field effect transistor (DG-CNTFET). The design is based on a property specific to this device: ambivalence, enabling p-type or n-type behavior depending on the back-gate voltage. Using available models, CNT-DR8F is simulated and analyzed at 20GHz operation. The authors also gi...Show More
This paper presents the concept and the design of a new architecture for microfluxgate sensors. An innovative low-pass architecture based on pulsed excitation is presented, with a ΣΔ-based closed-loop measurement circuit including digital and semi-digital filters. While the total power consumption is reduced to about 20mW, it also allows a power/resolution tradeoff for a digitally-controlled tunab...Show More
The evolution of integrated circuit technology is causing system designs to move towards communication-based architectures. However, metallic interconnect networks can be very costly in terms of power and silicon area and can thus become a bottleneck in system on chip design. Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect ...Show More
This paper gives an overview of some potential uses of carbon nanotube field effect transistors (CNTFETs) in logic circuit design. The realization of existing logic functions with resistive-load and complementary logic is described, with some examples of how a logic function can be coded by selective doping of a single nanotube molecule. The exploitation of properties specific to CNTFETs to build ...Show More
The design and the optimization of a new VCO operating at 60GHz is detailed. This key block in millimeterwave transceivers takes advantage of a promising CMOS PDSOI technology on a high-resistivity substrate (p>1000ω.cm). As a result, an innovative architecture has been chosen to overcome difficulties encountered in the classical LC tank structure. One of the major issues in microwave networks is ...Show More
This paper presents a heterogeneous model of an optical network-on chip (ONoC). An ONoC is an optical interconnect architecture integrated on a system-on-chip, and is intended to replace traditional electrical networks-on-chip (NoC) to overcome their future bandwidth limitations. To evaluate the advantages of a technological implementation of an ONoC, it is necessary to model its behavior and to r...Show More
This paper presents the design of a multi-phase voltage-controlled oscillator (VCO) in CMOS/SOI technology, based on a ring amplifier with LC resonators. This circuit is a key block of a 40 Gbit/s serial communications system. Operating at a speed of one-fourth of the nominal data rate, this CMOS architecture complies with SONET OC-768 standard. The circuit exhibits a 25% frequency tuning range fr...Show More
We present a passive novel optical add-drop filter incorporating microdisk resonators, in complementary metal-oxide-semiconductor compatible silicon-on-insulator technology, which enables a simple layout of complex optical networks-on-chip. The measured properties of the fabricated devices are in agreement with theory, established using the time-domain coupled mode theory and finite-difference tim...Show More
This paper discusses the 10 GHz low phase noise fully integrated VCOs in 130 nm high resistivity CMOS/SOI for 40 Gbits/s datacom. This work is a first step towards the evaluation of SOI technology for 40 Gbit/s applications. In particular, CMOS/SOI technologies allow the design of high speed, high performance VCOs and key blocks for high data rate designs. Useful advantages over bulk processes (es...Show More
In this paper, we present a framework for the automated design of integrated multi-domain systems. The platform allows the designer to set optimization problems according to a hierarchical decomposition strategy, define complex specification functions for each block at a given hierarchical level, follow the progress of optimization and finally view results. Encapsulation of design methodologies is...Show More
In this paper, we present a tool to analyze photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical simulator, based on the finite elements me...Show More
This paper presents a fast and robust design method for systematically maximising the frequency response of basic CMOS transimpedance amplifiers, a class of circuit of fundamental interest to architects of MOEMS/NOEMS. This method is based on a frequential analysis of the structure and a mapping of the component values to coefficients in a filter approximation function of Butterworth type. We use ...Show More
The use of optics is considered to be an alternative solution that could overcome the limitations of metallic interconnects. In this paper, we present a quantitative analysis of the performance gains of using optical interconnect for clock distribution in terms of power and frequency. We present detailed comparative simulations of the features of optical and electrical H-tree clock networks.Show More