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Jin-Hong Park - IEEE Xplore Author Profile
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Jin-Hong Park

Also published under: J. -H. Park

Publications
28
Citations
412
Publications by Year
20082023
Co-Authors:
Show All Co-Authors (83)
Image of author Jin-Hong Park

Jin-Hong Park

Also published under: J. -H. Park

Affiliation

Department of Electrical and Computer Engineering
Sungkyunkwan University
Suwon, Korea
SKKU Advanced Institute of Nanotechnology (SAINT)
Sungkyunkwan University
Suwon, Korea

Publication Topics

Biography

Jin-Hong Park received the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 2006 and 2009, respectively, with a specialization in physics and technology of low-temperature measurement and electrical characterization of Ge MOSFETs for monolithic 3D-IC applications.(Based on document published on 4 July 2017).
Publications
28
Citations
412
Publications by Year
20082023
Co-Authors:
Show All Co-Authors (83)
Author's Published Works

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WSe2 Field-effect Transistor with Electron-beam-induced W-shaped IV Characteristic and its Application to a Ternary NAND Gate

Maksim Andreev;Juncheol Kang;Taeran Lee;Jin-Hong Park

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Year: 2023 | Conference Paper |
We report WSe2 homojunction-based field-effect transistors (FETs) with W-shaped transfer IV characteristics, enabled by area-selective tailoring of the WSe2 channel work function with the electron-beam treatment. We demonstrate that FETs with such IV curves are suitable for the implementation of the two-input ternary NAND logic gate, one of the essential building blocks required for the realizatio...Show More

WSe2 Field-effect Transistor with Electron-beam-induced W-shaped IV Characteristic and its Application to a Ternary NAND Gate

Maksim Andreev;Juncheol Kang;Taeran Lee;Jin-Hong Park

Year: 2023 | Conference Paper |

In-Depth Study of 3D Color-Resist Coating Process for Optically Uniform Image Sensors

Sungjun Kim;Jaesang Yoo;Hakyu Choi;Jaekwan Seo;Sunghun Lee;Sang Min Won;Jin-Hong Park;Keun Heo

IEEE Access
Year: 2021 | Volume: 9 | Journal Article |
Cited by: Papers (1)
The color filter required for manufacturing a CMOS image sensor was redeveloped to optimize its optical uniformity. An in-depth study of the three-dimensional (3D) coating process and how it gives rise to various radial-shaped striation patterns was conducted. These radial-shaped striation patterns were systematically investigated with reference to two types of patterns: the orthogonal type found ...Show More

In-Depth Study of 3D Color-Resist Coating Process for Optically Uniform Image Sensors

Sungjun Kim;Jaesang Yoo;Hakyu Choi;Jaekwan Seo;Sunghun Lee;Sang Min Won;Jin-Hong Park;Keun Heo

Year: 2021 | Volume: 9 | Journal Article |

An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications

Kyoungjin Lee;Haneul Kim;Jehyung Yoon;Hyoung-Seok Oh;Jin-Hong Park;Byeong-Ha Park;Hojin Park;Yoonmyung Lee

IEEE Transactions on Industrial Electronics
Year: 2020 | Volume: 67, Issue: 12 | Journal Article |
Cited by: Papers (6)
A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drives applications in portable devices, where standby mode efficiency with 100-mA load. To enhance efficiency in light load conditions and to achieve a wide operation load range, loss minimization by balancing conduction and switching losses is ado...Show More

An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications

Kyoungjin Lee;Haneul Kim;Jehyung Yoon;Hyoung-Seok Oh;Jin-Hong Park;Byeong-Ha Park;Hojin Park;Yoonmyung Lee

Year: 2020 | Volume: 67, Issue: 12 | Journal Article |

Highly Efficient Multilayer Rhenium Disulfide-Based Homo- and Hetero-Junction Photovoltaic Devices

Kwan-Ho Kim;Jaewoo Shim;Jin-Hong Park

2018 Conference on Lasers and Electro-Optics Pacific Rim (CLEO-PR)
Year: 2018 | Conference Paper |
Recently, transition-metal dichalcogenides (TMDs), such as molybdenum disulfide (MoS2)and tungsten diselenide (WSe2), have been studied for photovoltaic devices due to their superior optical properties[1] However, power conversion efficiency (PCE)of the devices, which were fabricated on the monolayer TMDs with direct bandgap property, has been limited because of mechanical limitation for absorbing...Show More

Highly Efficient Multilayer Rhenium Disulfide-Based Homo- and Hetero-Junction Photovoltaic Devices

Kwan-Ho Kim;Jaewoo Shim;Jin-Hong Park

Year: 2018 | Conference Paper |

Temperature-Dependent Electrical Characterization of Amorphous Indium Zinc Oxide Thin-Film Transistors

Keun Heo;Kyung-Sang Cho;Jun Young Choi;Sangmin Han;Yun Seop Yu;Yonmook Park;Gwangwe Yoo;Jin-Hong Park;Sung Woo Hwang;Sang Yeol Lee

IEEE Transactions on Electron Devices
Year: 2017 | Volume: 64, Issue: 8 | Journal Article |
Cited by: Papers (8)
In this study, N-type amorphous indium zinc oxide thin-film transistors are fabricated and temperature-dependent electrical characteristics in the range of 170-295 K are analyzed through experimental measurements and using an equivalent-circuit model. In this model, thermionic field emission for reverse bias and a thermionic emission mechanism for forward bias are applied. The barrier height coeff...Show More

Temperature-Dependent Electrical Characterization of Amorphous Indium Zinc Oxide Thin-Film Transistors

Keun Heo;Kyung-Sang Cho;Jun Young Choi;Sangmin Han;Yun Seop Yu;Yonmook Park;Gwangwe Yoo;Jin-Hong Park;Sung Woo Hwang;Sang Yeol Lee

Year: 2017 | Volume: 64, Issue: 8 | Journal Article |

Efficient Threshold Voltage Adjustment Technique by Dielectric Capping Effect on MoS2 Field-Effect Transistor

June Park;Dong-Ho Kang;Jong-Kook Kim;Jin-Hong Park;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2017 | Volume: 38, Issue: 8 | Journal Article |
Cited by: Papers (13)
In this letter, we demonstrate an efficient threshold voltage (Vth) adjustment technique by depositing single or double dielectric layers on MoS2 field-effect transistors (FETs). We used Al2O3 and SiO2 as the capping layers on the MoS2 FET and observed different average Vth shifts of -2.39 and +7.13 V, respectively. In order to further the controllability of the dielectric capping effect, the depo...Show More

Efficient Threshold Voltage Adjustment Technique by Dielectric Capping Effect on MoS2 Field-Effect Transistor

June Park;Dong-Ho Kang;Jong-Kook Kim;Jin-Hong Park;Hyun-Yong Yu

Year: 2017 | Volume: 38, Issue: 8 | Journal Article |

Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal–Interlayer–n-Germanium Source/Drain Structure

Gwang-Sik Kim;Gwangwe Yoo;Yujin Seo;Seung-Hwan Kim;Karam Cho;Byung Jin Cho;Changhwan Shin;Jin-Hong Park;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2016 | Volume: 37, Issue: 6 | Journal Article |
Cited by: Papers (12)
The effect of post-deposition H2 annealing (PDHA) on the reduction of a contact resistance by the metal-interlayer-semiconductor (M-I-S) source/drain (S/D) structure of the germanium (Ge) n-channel field-effect transistor (FET) is demonstrated in this letter. The M-I-S structure reduces the contact resistance of the metal/n-type Ge (n-Ge) contact by alleviating the Fermi-level pinning (FLP). In ad...Show More

Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal–Interlayer–n-Germanium Source/Drain Structure

Gwang-Sik Kim;Gwangwe Yoo;Yujin Seo;Seung-Hwan Kim;Karam Cho;Byung Jin Cho;Changhwan Shin;Jin-Hong Park;Hyun-Yong Yu

Year: 2016 | Volume: 37, Issue: 6 | Journal Article |

Non-Alloyed Ohmic Contacts on GaAs Using Metal-Interlayer-Semiconductor Structure With SF6 Plasma Treatment

Seung-Hwan Kim;Gwang-Sik Kim;Sun-Woo Kim;Jeong-Kyu Kim;Changhwan Choi;Jin-Hong Park;Rino Choi;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2016 | Volume: 37, Issue: 4 | Journal Article |
We demonstrate the effect of SF6 plasma passivation with a ZnO interlayer in a metal-interlayer-semiconductor (MIS) structure to reduce source/drain (S/D) contact resistance. The interface trap states and the metal-induced gap states causing the Fermi-level pinning problem are effectively alleviated by passivating the GaAs surface with SF6 plasma treatment and inserting a thin ZnO interlayer, resp...Show More

Non-Alloyed Ohmic Contacts on GaAs Using Metal-Interlayer-Semiconductor Structure With SF6 Plasma Treatment

Seung-Hwan Kim;Gwang-Sik Kim;Sun-Woo Kim;Jeong-Kyu Kim;Changhwan Choi;Jin-Hong Park;Rino Choi;Hyun-Yong Yu

Year: 2016 | Volume: 37, Issue: 4 | Journal Article |

Theoretical and Experimental Investigation of Graphene/High- $\kappa $ /p-Si Junctions

Jaewoo Shim;Gwangwe Yoo;Dong-Ho Kang;Woo-Shik Jung;Young-Chul Byun;Hyoungsub Kim;Won Tae Kang;Woo Jong Yu;Hyun-Yong Yu;Yongkook Park;Jin-Hong Park

IEEE Electron Device Letters
Year: 2016 | Volume: 37, Issue: 1 | Journal Article |
Cited by: Papers (4)
Here, we theoretically and experimentally investigate the impact of a high-κ layer inserted between graphene and p-Si in a graphene/Si junction. We have achieved 86-fold and 222-fold reductions in a specific contact resistivity (ρc) by inserting 1-nm-thick Al2O3 and 2-nm-thick TiO2 in the graphene-semiconductor junction, respectively, corresponding to lowering the effective barrier height by 0.24 ...Show More

Theoretical and Experimental Investigation of Graphene/High- $\kappa $ /p-Si Junctions

Jaewoo Shim;Gwangwe Yoo;Dong-Ho Kang;Woo-Shik Jung;Young-Chul Byun;Hyoungsub Kim;Won Tae Kang;Woo Jong Yu;Hyun-Yong Yu;Yongkook Park;Jin-Hong Park

Year: 2016 | Volume: 37, Issue: 1 | Journal Article |

Fermi-Level Unpinning Using a Ge-Passivated Metal–Interlayer–Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

Seung-Hwan Kim;Gwang-Sik Kim;Jeong-Kyu Kim;Jin-Hong Park;Changhwan Shin;Changhwan Choi;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2015 | Volume: 36, Issue: 9 | Journal Article |
We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer- semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-ind...Show More

Fermi-Level Unpinning Using a Ge-Passivated Metal–Interlayer–Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

Seung-Hwan Kim;Gwang-Sik Kim;Jeong-Kyu Kim;Jin-Hong Park;Changhwan Shin;Changhwan Choi;Hyun-Yong Yu

Year: 2015 | Volume: 36, Issue: 9 | Journal Article |

Surface Passivation of Germanium Using SF6 Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET

Gwang-Sik Kim;Seung-Hwan Kim;Jeong-Kyu Kim;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Byung Jin Cho;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2015 | Volume: 36, Issue: 8 | Journal Article |
Cited by: Papers (23)
We demonstrate Fermi-level unpinning and contact resistance reduction by surface passivation using SF6 plasma treatment of a metal/germanium (Ge) contact. A specific contact resistivity (Pc) of 1.14 × 10-3 Ω · cm2 and 0.31 eV of Schottky barrier height is achieved for a Ti/SF6-treated n-type Ge (n-Ge) (Nd = 1 × 1017 cm-3) contact, exhibiting 1700 times Pc reduction from a Ti/nontreated n-Ge contac...Show More

Surface Passivation of Germanium Using SF6 Plasma to Reduce Source/Drain Contact Resistance in Germanium n-FET

Gwang-Sik Kim;Seung-Hwan Kim;Jeong-Kyu Kim;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Byung Jin Cho;Hyun-Yong Yu

Year: 2015 | Volume: 36, Issue: 8 | Journal Article |

Controlling Grain Size and Continuous Layer Growth in Two-Dimensional MoS2 Films for Nanoelectronic Device Application

Jaeho Jeon;Sung Kyu Jang;Su Min Jeon;Gwangwe Yoo;Jin-Hong Park;Sungjoo Lee

IEEE Transactions on Nanotechnology
Year: 2015 | Volume: 14, Issue: 2 | Journal Article |
Cited by: Papers (18)
We report that control over the grain size and lateral growth of monolayer MoS2 film, yielding a uniform large-area monolayer MoS2 film, can be achieved by submitting the SiO2 surfaces of the substrates to oxygen plasma treatment and modulating substrate temperature in chemical vapor deposition (CVD) process. Scanning electron microscopy and atomic force microscopy images and Raman spectra reveale...Show More

Controlling Grain Size and Continuous Layer Growth in Two-Dimensional MoS2 Films for Nanoelectronic Device Application

Jaeho Jeon;Sung Kyu Jang;Su Min Jeon;Gwangwe Yoo;Jin-Hong Park;Sungjoo Lee

Year: 2015 | Volume: 14, Issue: 2 | Journal Article |

The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

Jeong-Kyu Kim;Gwang-Sik Kim;Hyohyun Nam;Changhwan Shin;Jin-Hong Park;Jong-Kook Kim;Byung Jin Cho;Krishna C. Saraswat;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2014 | Volume: 35, Issue: 12 | Journal Article |
Cited by: Papers (18)
We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n+-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal- semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S...Show More

The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

Jeong-Kyu Kim;Gwang-Sik Kim;Hyohyun Nam;Changhwan Shin;Jin-Hong Park;Jong-Kook Kim;Byung Jin Cho;Krishna C. Saraswat;Hyun-Yong Yu

Year: 2014 | Volume: 35, Issue: 12 | Journal Article |

Specific Contact Resistivity Reduction Through Ar Plasma-Treated TiO2−x Interfacial Layer to Metal/Ge Contact

Gwang-Sik Kim;Jeong-Kyu Kim;Seung-Hwan Kim;Jaesung Jo;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2014 | Volume: 35, Issue: 11 | Journal Article |
Cited by: Papers (34)
We demonstrate contact resistivity reduction by inserting an Ar plasma-treated TiO2-x heavily doped interfacial layer to metal/semiconductor contact to overcome a Fermi-level pinning problem on germanium (Ge). A specific contact resistivity of 3.16 × 10-3Ω · cm2 on moderately doped n-type Ge substrate (6 × 1016cm-3) was achieved, exhibiting ×584 reduction from Ti/Ge structure, and ×11 reduction fr...Show More

Specific Contact Resistivity Reduction Through Ar Plasma-Treated TiO2−x Interfacial Layer to Metal/Ge Contact

Gwang-Sik Kim;Jeong-Kyu Kim;Seung-Hwan Kim;Jaesung Jo;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Hyun-Yong Yu

Year: 2014 | Volume: 35, Issue: 11 | Journal Article |

Impacts of the Thermal Recovery Process on In–Ga–Zn–O (IGZO) TFTs

Seung-Ha Choi;Myung-Hoon Lim;Woo-Shik Jung;Jin-Hong Park

IEEE Electron Device Letters
Year: 2014 | Volume: 35, Issue: 8 | Journal Article |
Cited by: Papers (16)
In this letter, we investigate the impact of the thermal recovery (annealing) process on the electrical characteristics and the stability of IGZO TFTs in terms of: 1) vertical/lateral diffusion of Ti atoms into the IGZO channel region from the source/drain electrode and 2) recovery or local rearrangement of ions in IGZO. Although low thermal recovery temperatures <;300 °C are required to avoid the...Show More

Impacts of the Thermal Recovery Process on In–Ga–Zn–O (IGZO) TFTs

Seung-Ha Choi;Myung-Hoon Lim;Woo-Shik Jung;Jin-Hong Park

Year: 2014 | Volume: 35, Issue: 8 | Journal Article |

Analytical Study of Interfacial Layer Doping Effect on Contact Resistivity in Metal-Interfacial Layer-Ge Structure

Jeong-Kyu Kim;Gwang-Sik Kim;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Hyun-Yong Yu

IEEE Electron Device Letters
Year: 2014 | Volume: 35, Issue: 7 | Journal Article |
Cited by: Papers (22)
We present a new model to demonstrate the effect of heavily doped interfacial layer (IL) insertion on contact resistivity reduction in metal-germanium (Ge) structure. It is found that the doping of IL results in lowering Schottky barrier of Ge significantly, and based on this lowering effect, a metal-IL-semiconductor model is newly proposed. From this model, the abrupt reduction of contact resisti...Show More

Analytical Study of Interfacial Layer Doping Effect on Contact Resistivity in Metal-Interfacial Layer-Ge Structure

Jeong-Kyu Kim;Gwang-Sik Kim;Changhwan Shin;Jin-Hong Park;Krishna C. Saraswat;Hyun-Yong Yu

Year: 2014 | Volume: 35, Issue: 7 | Journal Article |

Germanium on insulator (GOI) structure locally grown on silicon using hetero epitaxial lateral overgrowth

J. H. Nam;W. S. Jung;J. Shim;T. Ito;Y. Nishi;J.-H. Park;K. C. Saraswat

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Year: 2013 | Conference Paper |
Cited by: Papers (1)
A CMOS compatible technique for fabricating germanium (Ge) on insulator (GOI) structure that is locally implemented on silicon (Si) substrate is demonstrated. On a (100) crystalline Si substrate, silicon dioxide (SiO2) is thermally grown. Then growth window for Ge is defined by locally etching down the SiO2 to reveal the Si surface. Ge is grown epitaxially with multiple steps of high temperature h...Show More

Germanium on insulator (GOI) structure locally grown on silicon using hetero epitaxial lateral overgrowth

J. H. Nam;W. S. Jung;J. Shim;T. Ito;Y. Nishi;J.-H. Park;K. C. Saraswat

Year: 2013 | Conference Paper |

Hydrazine-Based Fermi-Level Depinning Process on Metal/Germanium Schottky Junction

Hyun-Wook Jung;Woo-Shik Jung;Jin-Hong Park

IEEE Electron Device Letters
Year: 2013 | Volume: 34, Issue: 5 | Journal Article |
Cited by: Papers (5)
In this letter, we propose a hydrazine (N2H4)-based nitridation process, which reduces the native oxide (GeOx) component and finally transforms it into GeOxNy on intrinsic Ge, to relieve the EF pinning problem. The decomposition of GeOx and formation of GeOxNy by N2H4 are systematically investigated through cross-sectional transmission electron microscopy, X-ray photoelectron spectroscopy, and ato...Show More

Hydrazine-Based Fermi-Level Depinning Process on Metal/Germanium Schottky Junction

Hyun-Wook Jung;Woo-Shik Jung;Jin-Hong Park

Year: 2013 | Volume: 34, Issue: 5 | Journal Article |

Effects of Thermal Annealing on In Situ Phosphorus-Doped Germanium $\hbox{n}^{+}/\hbox{p}$ Junction

Jaewoo Shim;I. Song;W.-S. Jung;J. Nam;J. W. Leem;J. S. Yu;D. E. Kim;W. J. Cho;Y. S. Kim;D.-H. Jun;J. Heo;W. Park;Jin-Hong Park;K. C. Saraswat

IEEE Electron Device Letters
Year: 2013 | Volume: 34, Issue: 1 | Journal Article |
Cited by: Papers (7)
In this letter, we investigate the electrical behavior of vacancy $V_{\rm Ge}$ defects in Ge at various thermal annealing conditions through electrochemical capacitance–voltage analysis. Then, the effects of the annealing process on Ge $\hbox{n}^{+}/\hbox{p}$ junction diodes were also studied with $J{-}V$, transmission electron microscopy, and secondary ion mass spectroscopy measurements in the ...Show More

Effects of Thermal Annealing on In Situ Phosphorus-Doped Germanium $\hbox{n}^{+}/\hbox{p}$ Junction

Jaewoo Shim;I. Song;W.-S. Jung;J. Nam;J. W. Leem;J. S. Yu;D. E. Kim;W. J. Cho;Y. S. Kim;D.-H. Jun;J. Heo;W. Park;Jin-Hong Park;K. C. Saraswat

Year: 2013 | Volume: 34, Issue: 1 | Journal Article |

Characterization of Geometric Leakage Current of $ \hbox{GeO}_{2}$ Isolation and Effect of Forming Gas Annealing in Germanium p-n Junctions

Woo-Shik Jung;Jin-Hong Park;J.-Y. Jason Lin;Simon Wong;Krishna C. Saraswat

IEEE Electron Device Letters
Year: 2012 | Volume: 33, Issue: 11 | Journal Article |
Cited by: Patents (1)
In this letter, we have analyzed the area, perimeter, and corner leakage current components of lateral p+/n-Ge-based diodes with a GeO2 isolation layer, which were fabricated at temperatures below 500 °C. In addition, the effects of forming gas anneal are included, which was done to further reduce the leakage current. It was found that corner leakage was the most dominant source of surface leakage...Show More

Characterization of Geometric Leakage Current of $ \hbox{GeO}_{2}$ Isolation and Effect of Forming Gas Annealing in Germanium p-n Junctions

Woo-Shik Jung;Jin-Hong Park;J.-Y. Jason Lin;Simon Wong;Krishna C. Saraswat

Year: 2012 | Volume: 33, Issue: 11 | Journal Article |

Characteristics of Ultrashallow Hetero Indium–Gallium–Zinc–Oxide/Germanium Junction

Juhyeon Shin;Jaewoo Shim;Jongtaek Lee;Seung-Ha Choi;Woo-Shik Jung;Hyun-Yong Yu;Yonghan Roh;Jin-Hong Park

IEEE Electron Device Letters
Year: 2012 | Volume: 33, Issue: 10 | Journal Article |
Cited by: Papers (2)
In this letter, we demonstrate an n-indium-gallium-zinc-oxide (IGZO)/i-germanium (Ge) heterojunction diode with an ultrashallow junction depth of ~ 37 nm. X-ray diffraction, atomic force microscopy, and secondary ion mass spectrometry analyses are performed to precisely investigate the n-IGZO and n-IGZO/i-Ge junctions. When the junction diodes are annealed at between 400 °C and 600 °C, a very high...Show More

Characteristics of Ultrashallow Hetero Indium–Gallium–Zinc–Oxide/Germanium Junction

Juhyeon Shin;Jaewoo Shim;Jongtaek Lee;Seung-Ha Choi;Woo-Shik Jung;Hyun-Yong Yu;Yonghan Roh;Jin-Hong Park

Year: 2012 | Volume: 33, Issue: 10 | Journal Article |

Selective-Area High-Quality Germanium Growth for Monolithic Integrated Optoelectronics

Hyun-Yong Yu;Jin-Hong Park;Ali K. Okyay;Krishna C. Saraswat

IEEE Electron Device Letters
Year: 2012 | Volume: 33, Issue: 4 | Journal Article |
Cited by: Papers (17)
Selective-area germanium (Ge) layer on silicon (Si) is desired to realize the advanced Ge devices integrated with Si very-large-scale-integration (VLSI) components. We demonstrate the area-dependent high-quality Ge growth on Si substrate through SiO2 windows. The combination of area-dependent growth and multistep deposition/hydrogen annealing cycles has effectively reduced the surface roughness an...Show More

Selective-Area High-Quality Germanium Growth for Monolithic Integrated Optoelectronics

Hyun-Yong Yu;Jin-Hong Park;Ali K. Okyay;Krishna C. Saraswat

Year: 2012 | Volume: 33, Issue: 4 | Journal Article |

Optimization of Germanium (Ge) $\hbox{n}^{+}/\hbox{p}$ and $\hbox{p}^{+}/\hbox{n}$ Junction Diodes and Sub 380 $^{\circ}\hbox{C}$ Ge CMOS Technology for Monolithic Three-Dimensional Integration

Jin-Hong Park;Duygu Kuzum;Hyun-Yong Yu;Krishna C. Saraswat

IEEE Transactions on Electron Devices
Year: 2011 | Volume: 58, Issue: 8 | Journal Article |
Cited by: Papers (7)
In this paper, we optimize and investigate Ge n+/p and p+/n junction diodes formed by Co metal-induced dopant activation technique at the activation temperature range between 300 °C and 420 °C in terms of on/ off-current ratio. Combining this low-temperature n+/p and p+/n junction formation technique with a low-temperature gate stack comprised of Al/Al2O3/GeO2 by ozone oxidation technique, we demo...Show More

Optimization of Germanium (Ge) $\hbox{n}^{+}/\hbox{p}$ and $\hbox{p}^{+}/\hbox{n}$ Junction Diodes and Sub 380 $^{\circ}\hbox{C}$ Ge CMOS Technology for Monolithic Three-Dimensional Integration

Jin-Hong Park;Duygu Kuzum;Hyun-Yong Yu;Krishna C. Saraswat

Year: 2011 | Volume: 58, Issue: 8 | Journal Article |

The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics

Duygu Kuzum;Jin-Hong Park;Tejas Krishnamohan;H.-S. Philip Wong;Krishna C. Saraswat

IEEE Transactions on Electron Devices
Year: 2011 | Volume: 58, Issue: 4 | Journal Article |
Cited by: Papers (57)
In this paper, the acceptor and donor nature of interface traps are investigated using conductance and interface trap time constant measurements on Ge n- and p-type metal-oxide-semiconductor field-effect transistors (N-and PMOSFETs). The presence of acceptor-type interface trap states in the valence-band side of Ge band gap is confirmed by these measurements. Electron trapping by the acceptor-type...Show More

The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics

Duygu Kuzum;Jin-Hong Park;Tejas Krishnamohan;H.-S. Philip Wong;Krishna C. Saraswat

Year: 2011 | Volume: 58, Issue: 4 | Journal Article |

Novel Germanium n-MOSFETs With Raised Source/Drain on Selectively Grown Ge on Si for Monolithic Integration

Hyun-Yong Yu;Masaharu Kobayashi;Jin-Hong Park;Yoshio Nishi;Krishna C. Saraswat

IEEE Electron Device Letters
Year: 2011 | Volume: 32, Issue: 4 | Journal Article |
Cited by: Papers (11)
We demonstrate novel Ge n-MOSFETs with raised source/drain (S/D) fabricated on high-quality single-crystal Ge selectively grown heteroepitaxially on Si. For the raised S/D, an implant-free in situ doping technique has been employed for low-resistance, abrupt, and shallow $\hbox{n}^{+}/\hbox{p}$ junctions. The novel n-MOSFETs show an excellent on/off ratio $(\hbox{4} \times \hbox{10}^{3})$ with ver...Show More

Novel Germanium n-MOSFETs With Raised Source/Drain on Selectively Grown Ge on Si for Monolithic Integration

Hyun-Yong Yu;Masaharu Kobayashi;Jin-Hong Park;Yoshio Nishi;Krishna C. Saraswat

Year: 2011 | Volume: 32, Issue: 4 | Journal Article |

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