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Isothermal fatigue tests of plastic ball grid array (PBGA) SnAgCu lead-free solder joints at 60/spl deg/C
56th Electronic Components and Technology Conference 2006
Year: 2006 | Conference Paper |
A new thermal-fatigue life prediction equation for a plastic ball grid array (PBGA) package with 95.5wt%Sn4.0wt%Ag0.5wt%Cu lead-free solder balls is proposed in this investigation. The test vehicle consists of the PBGA package, a lead-free PCB, and a lead-free solder paste (95.5wt%Sn3.9wt%Ag0.6wt%Cu). The coefficients of the fatigue equation presented herein are determined by best fit of the test ...Show More
Thermal stress analysis of a flip-chip parallel VCSEL (vertical-cavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints
56th Electronic Components and Technology Conference 2006
Year: 2006 | Conference Paper |
Solders such as the 48wt%Sn-52wt%In, 42wt%Sn-58wt%Bi, 63wt%Sn-37wt%Pb, Sn(3-4)wt%Ag(0.5-0.7)wt%Cu, and 80wt%Au-20wt%Sn, are studied as interconnect materials in a vertical-cavity surface-emitting laser (VCSEL). The Sn52In alloy is a low temperature (melting point = 118degC) lead-free solder and a potential candidate material for this device. In this study, thermal-structural analysis evaluates the...Show More
Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints
Proceedings Electronic Components and Technology, 2005. ECTC '05.
Year: 2005 | Conference Paper |
Cited by: Papers (13)
Thermal-fatigue life prediction equation for wafer-level chip scale package (WLCSP) lead-free solder joints on lead-free printed circuit board (PCB)
J.H. Lau;Dongkai Shangguan;D.C.Y. Lau;T.T.W. Kung;S.W.R. Lee
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)
Year: 2004 | Conference Paper |
Cited by: Papers (6)
A new thermal-fatigue life prediction equation for a class of lead-free solder alloys, 95.5wt%Sn3.9-4.0wt%Ag0.5-0.6wt%Cu is proposed in this investigation. The test vehicle consists of a lead-free solder-bumped WLCSP, lead-free PCB, and lead-free solder paste. The coefficients of the fatigue equation presented herein are determined by best fitted with the isothermal fatigue data of the test vehicl...Show More
Reliability testing and data analysis of an 1657CCGA (ceramic column grid array) package with lead-free solder paste on lead-free PCBs (printed circuit boards)
J. Lau;W. Dauksher;E. Ott;D. Shangguan;J. Smetana;R. Horsley;T. Castello;D. Love;I. Menis;B. Sullivan
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)
Year: 2004 | Conference Paper |
Cited by: Papers (3)
In this study, the thermal cycling test of the 1657CCGA package with 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb solder pastes on lead-free PCBs with HASL (hot-air solder leveling) CuSn, NiAu (electroless Ni and immersion Au, ENIG), and Entek OSP (organic solderability preservative) surface finishes are performed. The test stopped at 7500 cycles (0 to 100/spl deg/C, 40-minute cycle). The test dat...Show More
Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates
In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these under...Show More
Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability
Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia bu...Show More
Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board
In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to ob...Show More
Effects of voids on bump chip carrier (BCC++) solder joint reliability
52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)
Year: 2002 | Conference Paper |
Cited by: Papers (14)
In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack grow...Show More
Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)
The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow...Show More
Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)
2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)
Year: 2001 | Conference Paper |
Cited by: Papers (1)
The effect of a 2-layer microvia build-up printed circuit board (PCB) on the solder joint reliability of a wafer level chip scale package (WLCSP) assembly subject to thermal cycling is investigated in this study. The 62Sn-2Ag-36Pb solder joints are assumed to be: (1) an elastic material; (2) an elastic-plastic material; and (3) a creep material described by the Garofalo-Arrhenius creep constitutiv...Show More
Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mec...Show More
Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates
Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)
Year: 2000 | Conference Paper |
Cited by: Papers (3)
In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these under...Show More
Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability
Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)
Year: 2000 | Conference Paper |
Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers o...
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First Page of the Article
Show MoreReliability of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag lead-free solder joints on build-up microvia printed circuit board
International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)
Year: 2000 | Conference Paper |
Cited by: Papers (1)
In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale packages (WLCSP) on microvia build-up printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5 wt.%Sn-3.5 wt.%Ag. The 62 wt.%Sn-36 wt.%Pb-2 wt.%Ag solder is also considered to establish a baseline. These two sold...Show More
Creep analysis of solder bumped direct chip attach (DCA) on microvia build-up printed circuit board with underfill
International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)
Year: 2000 | Conference Paper |
Cited by: Papers (3)
The creep analysis of solder-bumped flip-chip on microvia build-up printed circuit board (PCB) with underfill encapsulant subjected to thermal cycling conditions are presented. Emphasis is placed on the effects of the conventional PCB's additional microvia build-up circuits on the solder joint reliability of the direct chip attach (DCA) assembly. The 62Sn-36Pb-2Ag solder joints are assumed to obey...Show More
Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)
International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)
Year: 2000 | Conference Paper |
Cited by: Papers (9)
The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the conventional PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are as...Show More
Taguchi design of experiment for wafer bumping by stencil printing
Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8 in) wafer by the stencil printing method. These factors are: paste types, squeeze forces, snap-off heights, aperture shapes, and aspect ratios. They are varied to form a two-level L8 orthogonal array experiment. Analysis of mean (ANOM) and analysis of variance (ANOVA) are us...Show More
Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants
Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five differe...Show More
Taguchi design of experiment for wafer bumping by stencil printing
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)
Year: 2000 | Conference Paper |
Cited by: Papers (4)
Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8") wafer by stencil printing method. These factors are: paste types (type 3 and type 4), squeeze forces (9 and 12 lbs.), snap-off heights (0 and 5 mils), aperture shapes (square and circle), and aspect ratios (2.5 and 2.75). They are varied to form a two-level L8 orthogonal a...Show More
Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)
Year: 2000 | Conference Paper |
Cited by: Papers (16)
The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mec...Show More
Cost analysis: solder bumped flip chip versus wire bonding
The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided.Show More
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