Ramsis Girgis - IEEE Xplore Author Profile

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Author details

Ramsis Girgis

Also published under: R. S. Girgis, Ramsis S. Girgis, R. Girgis

Publications

50

Citations

586

Publications by Year

19832022

Co-Authors:

A. H. Al-HajD. AllenJ. AngerBob ArrittC. J. Baldwin

Show All Co-Authors (54)

Ramsis Girgis

Also published under: R. S. Girgis, Ramsis S. Girgis, R. Girgis

Affiliation

Hitachi Energy

Saint Louis

MO, USA

Publication Topics

Transformative Power,
Transformer Design,
Core Type,
Formation Of Core,
Hot Temperature,
Shell Form,
Transformer Winding,
Core Shell,
Evaluation Of Capability,
Flux-cored,
High Frequency Components,
Highest Peak

Biography

Dr. Ramsis S. Girgis (Life member 2011) is presently the Research & Development manager at the Hitachi Energy group in St. Louis, Missouri. He is also the leader of the global Hitachi Energy R&D activities in the area of “Transformer Core Performance” and Co - Leader of the global Hitachi Energy R&D activities in the “Transformer Noise” area.,Dr. Girgis received his Ph.D. degree from the University of Saskatchewan, Canada, in Electrical Engineering in 1978. He has over 45 years of R&D experience in the area of power, distribution, and high frequency transformers, rotating machines, and pulse power components. He has published and presented over 80 scientific papers in IEEE, IEE, CIGRE, and other international journals. He is presently the c...

Publications

50

Citations

586

Publications by Year

19832022

Co-Authors:

A. H. Al-Haj
D. Allen
J. Anger
Bob Arritt
C. J. Baldwin

Show All Co-Authors (54)

Author's Published Works

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Showing 1-25 of 124 results

Conferences (75)

Journals (41)

Magazines (8)

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Jaydeep P. Kulkarni(95)
Kaushik Roy(22)
Jaydeep Kulkarni(20)
Vivek De(18)
Meizhi Wang(16)
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA(14)
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA(12)
Intel, Hillsboro, OR(10)
Circuit Research Laboratory, Intel Corporation, Hillsboro, OR, USA(8)
University of Texas, Austin, TX(6)
IEEE Journal of Solid-State Circuits(13)
IEEE Transactions on Electron Devices(11)
IEEE Solid-State Circuits Magazine(6)
2021 IEEE Custom Integrated Circuits Conference (CICC)(4)
2022 Device Research Conference (DRC)(4)
IEEE(124)
San Francisco, CA, USA(20)
Austin, TX, USA(5)
San Jose, CA, USA(5)
Columbus, OH, USA(4)
Orlando, FL, USA(4)
Low Voltage(28)
Static Random Access Memory(27)
Area Overhead(24)
Read Operation(24)
Energy Efficiency(20)

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Results

Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping

Yixin Qin;Saikat Chakraborty;Zijian Zhao;Kijoon Kim;Suhwan Lim;Jongho Woo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Asif Khan;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

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In this work, we performed a comprehensive experimental and modeling study, clarifying the role of ferroelectric materials in boosting the memory window of FeFETs with gate-side charge injection for the first time. We separated the ferroelectric contributions to the memory window into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: (i) Ferroelectric ma...Show More

Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping

Yixin Qin;Saikat Chakraborty;Zijian Zhao;Kijoon Kim;Suhwan Lim;Jongho Woo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Asif Khan;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni

2024 IEEE International Electron Devices Meeting (IEDM)

Year: 2024 | Conference Paper |

Optimization of Complementary Reconfigurable Field-Effect Transistor for Improved Circuit-Level Metrics

Juhan Ahn;Saroj Satapathy;Jaydeep P. Kulkarni

2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Year: 2024 | Conference Paper |

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The Reconfigurable Field-Effect Transistor (RFET) enables dual-mode (n-type and p-type) operation in a single device, enhancing circuit design efficiency. However, conventional silicon-based RFETs often exhibit low saturation currents, which restrict their application in high-performance circuits. In this study, the Complementary RFET (CRFET) was studied to overcome this limitation by optimizing p...Show More

Optimization of Complementary Reconfigurable Field-Effect Transistor for Improved Circuit-Level Metrics

Juhan Ahn;Saroj Satapathy;Jaydeep P. Kulkarni

2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Year: 2024 | Conference Paper |

Data Movement-Aware, Ping-Pong Ising Machine Supporting Full Connectivity and Variable Bitwidths

Chieh-Pu Lo;Sirish Oruganti;Yipeng Wang;Mengtian Yang;Shanshan Xie;Jaydeep P. Kulkarni

2024 IEEE European Solid-State Electronics Research Conference (ESSERC)

Year: 2024 | Conference Paper |

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Ising computation is an emerging paradigm for efficiently solving the time-consuming Combinatorial Optimization problems (COP). In particular, Compute-In-Memory (CIM) based Ising machines are promising for Hamiltonian computations capturing the spin state dynamics using a dense memory array. However, the advancement of CIM-based Ising machines for accurately solving complex COPs is limited by the ...Show More

Data Movement-Aware, Ping-Pong Ising Machine Supporting Full Connectivity and Variable Bitwidths

Chieh-Pu Lo;Sirish Oruganti;Yipeng Wang;Mengtian Yang;Shanshan Xie;Jaydeep P. Kulkarni

2024 IEEE European Solid-State Electronics Research Conference (ESSERC)

Year: 2024 | Conference Paper |

Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers

Juhan Ahn;Saroj Satapathy;Jaydeep P. Kulkarni

2024 Device Research Conference (DRC)

Year: 2024 | Conference Paper |

Cited by: Papers (1)

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The reconfigurable field-effect transistor (RFET) can exhibit both n-type and p-type transistor functionalities simultaneously [1] , offering enhanced flexibility in circuit design. At the expense of increased device size due to additional gates, multiple functions can be integrated within the same footprint, or equivalent functionality can be achieved with fewer device counts, and improved flexib...Show More

Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers

Juhan Ahn;Saroj Satapathy;Jaydeep P. Kulkarni

2024 Device Research Conference (DRC)

Year: 2024 | Conference Paper |

Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications

Saikat Chakraborty;Jaydeep P. Kulkarni

2024 Device Research Conference (DRC)

Year: 2024 | Conference Paper |

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Gated thyristor-based single transistor (1-T) dynamic RAM (TRAM) is a promising candidate as cache memory for high-performance computing (HPC) systems at cryogenic temperatures [1] . Its large ON/OFF ratio offers fast read/write speed; low operating voltage, long retention, and non-destructive read operation lead to very low power consumption; and the FinFET compatible 1-T cell structure enables h...Show More

Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications

Saikat Chakraborty;Jaydeep P. Kulkarni

2024 Device Research Conference (DRC)

Year: 2024 | Conference Paper |

Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks

Sumanth N. Karanth;Sirish Oruganti;Meizhi Wang;Jaydeep P. Kulkarni

2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Year: 2024 | Conference Paper |

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This work aims to enhance the hardware security of mixed-signal circuits, particularly Successive Approximation Register Analog-to-Digital Converters (SAR-ADCs), through the introduction of an innovative circuit technique aimed at bolstering their resistance against power side-channel attacks (PSCAs). A comprehensive mathematical analysis of PSCAs targeting SARADCs is undertaken, with specific emp...Show More

Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks

Sumanth N. Karanth;Sirish Oruganti;Meizhi Wang;Jaydeep P. Kulkarni

2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

Year: 2024 | Conference Paper |

CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems

Mengtian Yang;Yipeng Wang;Shanshan Xie;Chieh-Pu Lo;Meizhi Wang;Sirish Oruganti;Rishabh Sehgal;Jaydeep P. Kulkarni

2024 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2024 | Conference Paper |

Cited by: Papers (1)

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Integer Linear Programming (ILP) is an NP-complete combinatorial optimization problem (COP), suggesting that it is computationally challenging to solve due to its exponentially increased operations with scaling. As shown in Fig. 1, The ILP is relevant in various real-world scenarios such as computational biology [1], investment decision, automated driving, and electronic design automation [2]. An ...Show More

CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems

Mengtian Yang;Yipeng Wang;Shanshan Xie;Chieh-Pu Lo;Meizhi Wang;Sirish Oruganti;Rishabh Sehgal;Jaydeep P. Kulkarni

2024 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2024 | Conference Paper |

SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture

Siddhartha Raman Sundara Raman;Lizy K. John;Jaydeep P. Kulkarni

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

Year: 2024 | Conference Paper |

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Recently there have been efforts to solve difficult computation problems harnessing or drawing inspiration from nature. A prominent example is the use of Ising machines for solving NP-complete problems [1], [23]. Ising machines have evolved from quantum/optical annealers and oscillator-based designs [1] to the recent CMOS-based Von-Neumann [36]/in-memory designs [35]. While prior works have demons...Show More

SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture

Siddhartha Raman Sundara Raman;Lizy K. John;Jaydeep P. Kulkarni

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

Year: 2024 | Conference Paper |

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits

Sirish Oruganti;Meizhi Wang;Vishnuvardhan V. Iyer;Yipeng Wang;Mengtian Yang;Raghavan Kumar;Sanu K. Mathew;Jaydeep P. Kulkarni

2024 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2024 | Conference Paper |

Cited by: Papers (1)

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Cryptographic hardware modules, by exhibiting unique power and EM signatures, are vulnerable to Side Channel Attacks (SCAs) revealing secret keys. Prior countermeasures based on power port [1] –[4] and masking [5] incur significant area and power overheads or are often not amenable to scaling and ASIC flow integration. Prior work on clock port randomization [6] can cause SoC timing verification an...Show More

Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits

Sirish Oruganti;Meizhi Wang;Vishnuvardhan V. Iyer;Yipeng Wang;Mengtian Yang;Raghavan Kumar;Sanu K. Mathew;Jaydeep P. Kulkarni

2024 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2024 | Volume: 67 | Conference Paper |

30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing

Yipeng Wang;Mengtian Yang;Chieh-Pu Lo;Jaydeep P. Kulkarni

2024 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2024 | Conference Paper |

Cited by: Papers (1)

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Vector processors have re-emerged in high-performance computing and flagship mobile SoC designs for their improved programmability, appealing power efficiency over multicore processors and area efficiency over GPUs [1]. For modern data-parallel tasks (ML, DSP, vision), vector processors can approach the efficiency of custom designs, while maintaining the flexibility of CPUs and GPUs. However, ther...Show More

30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing

Yipeng Wang;Mengtian Yang;Chieh-Pu Lo;Jaydeep P. Kulkarni

2024 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2024 | Volume: 67 | Conference Paper |

Comprehensive TCAD-Based Retention Study of Thyristor RAM (TRAM) for Low-Power and High-Speed Cryogenic Memory Applications

Saikat Chakraborty;Jaydeep P. Kulkarni

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 2 | Journal Article |

Cited by: Papers (2)

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A capacitor-less 1-T dynamic random access memory (DRAM) cell based on a thin capacitively coupled thyristor (TRAM) is analyzed across a wide temperature range from 300 K down to 77 K through comprehensive Technology Computer-Aided Design (TCAD) simulations for large capacity, high-speed, and low-voltage cryogenic cache memory applications. Different data-loss mechanisms, including Shockley-Read-H...Show More

Comprehensive TCAD-Based Retention Study of Thyristor RAM (TRAM) for Low-Power and High-Speed Cryogenic Memory Applications

Saikat Chakraborty;Jaydeep P. Kulkarni

IEEE Transactions on Electron Devices

Year: 2024 | Volume: 71, Issue: 2 | Journal Article |

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

Shanshan Xie;Can Ni;Aseem Sayal;Pulkit Jain;Fatih Hamzaoglu;Jaydeep P. Kulkarni

IEEE Journal of Solid-State Circuits

Year: 2024 | Volume: 59, Issue: 6 | Journal Article |

Cited by: Papers (4)

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This article presents a compute-in-memory (CIM) architecture for a large-scale machine learning (ML) accelerator, which employs $1T1C$ embedded dynamic random access memory (eDRAM) bitcells as charge domain circuits for convolution neural network (CNN) multiply-accumulation-averaging (MAV) computations. By repurposing existing $1T1C$ eDRAM columns to construct an adaptive data converter, dot-p...Show More

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

Shanshan Xie;Can Ni;Aseem Sayal;Pulkit Jain;Fatih Hamzaoglu;Jaydeep P. Kulkarni

IEEE Journal of Solid-State Circuits

Year: 2024 | Volume: 59, Issue: 6 | Journal Article |

A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication

Mengtian Yang;Yipeng Wang;Jaydeep P. Kulkarni

2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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The computational demands for recent large transformer- based language models and Neural Radiance Fields (NeRF) have rapidly increased, impacting applications like conversational AI and Mixed Reality (MR). Current accelerator architectures struggle to cope with the vast computational requirements, creating a gap with slowly growing hardware resources. This paper proposes repurposing memory compone...Show More

A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication

Mengtian Yang;Yipeng Wang;Jaydeep P. Kulkarni

2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC)

Year: 2023 | Conference Paper |

RI-SAR: Randomized Input SAR ADC Resilient to Power Side Channel Attacks

Sumanth N. Karanth;Sirish Oruganti;Meizhi Wang;Jaydeep P. Kulkarni

2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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Analog-to-Digital Converters (ADCs) are vital components in sensor systems, responsible for converting analog signals into digital representations. However, studies have highlighted the susceptibility of ADCs to side-channel attacks, such as Power Side Channel Attacks (PSCAs) and Electromagnetic Side Channel Attacks (EM-SCAs), which compromise the confidentiality and integrity of the system. In th...Show More

RI-SAR: Randomized Input SAR ADC Resilient to Power Side Channel Attacks

Sumanth N. Karanth;Sirish Oruganti;Meizhi Wang;Jaydeep P. Kulkarni

2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)

Year: 2023 | Conference Paper |

CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor

Yipeng Wang;Mengtian Yang;Shanshan Xie;Meizhi Wang;Jaydeep P Kulkarni

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)

Year: 2023 | Conference Paper |

Cited by: Papers (2)

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This paper presents the first Compute-in-memory (CIM) Graph Neural Networks (GNN) processor, CIMGN, running complete GNN inference blocks with up to 16-bit precession. Accelerating GNN is more challenging than DNN for its combination of compute-bounded Transformation and memory-bounded Aggregation, which leads to low efficiency and low bandwidth utilization on traditional architecture. CIMGN uses ...Show More

CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor

Yipeng Wang;Mengtian Yang;Shanshan Xie;Meizhi Wang;Jaydeep P Kulkarni

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)

Year: 2023 | Conference Paper |

Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines

Rishabh Sehgal;Rishab Mehra;Can Ni;Jaydeep P. Kulkarni

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)

Year: 2023 | Conference Paper |

Cited by: Papers (2)

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An energy-efficient and high-density first-ever Read Only Memory (ROM) based compute-in-memory (CIM) design for edge AI inference is demonstrated featuring 1) MultiLevel-Cell (MLC) using standard via-programed ROM bitcell; 2) Source-Line PMOS current driving; 3) Auto-scaling diode-connected current-to-voltage (I2V) converters; 4) 3-b ADC with ROM-based VREF generation; 5) Early termination of conv...Show More

Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines

Rishabh Sehgal;Rishab Mehra;Can Ni;Jaydeep P. Kulkarni

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)

Year: 2023 | Conference Paper |

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges

S. S. Teja Nibhanupudi;Sirish Oruganti;Rahul Mathur;Nishant Gupta;Meizhi Wang;Jaydeep P. Kulkarni

2023 60th ACM/IEEE Design Automation Conference (DAC)

Year: 2023 | Conference Paper |

Cited by: Papers (2)

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Buried power rails and back-side power grids are promising technology-scaling boosters for advanced CMOS technology nodes. System-level evaluation of these technologies shows tremendous promise from power-performance-area (PPA), IR drop, and dynamic voltage droop perspective. However, several process, device, and architectural challenges must be addressed to realize the full potential of this tech...Show More

Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges

S. S. Teja Nibhanupudi;Sirish Oruganti;Rahul Mathur;Nishant Gupta;Meizhi Wang;Jaydeep P. Kulkarni

2023 60th ACM/IEEE Design Automation Conference (DAC)

Year: 2023 | Conference Paper |

Security Robustness of Buried Power Rail Interconnect Technology: Modeling, Analysis and Countermeasures

Sirish Oruganti;Nishant Gupta;SS Teja Nibhanupudi;Meizhi Wang;Jaydeep P. Kulkarni

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

Year: 2023 | Conference Paper |

Cited by: Papers (1)

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Technology scaling gives rise to challenges in efficient power delivery for sub-5nm nodes. Buried Power Rail (BPR) interconnect technology is a promising solution for efficient monolithic power delivery. It provides power-performance-area (PP A) metric gains without actual dimensional scaling. With the introduction of any new technology, it is important to characterize it for potential security th...Show More

Security Robustness of Buried Power Rail Interconnect Technology: Modeling, Analysis and Countermeasures

Sirish Oruganti;Nishant Gupta;SS Teja Nibhanupudi;Meizhi Wang;Jaydeep P. Kulkarni

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)

Year: 2023 | Conference Paper |

A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce

Yipeng Wang;Shanshan Xie;Jacob Rohan;Meizhi Wang;Mengtian Yang;Sirish Oruganti;Jaydeep P. Kulkarni

2023 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2023 | Conference Paper |

Cited by: Papers (4)

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Graph Neural Networks (GNN) recently find many exciting applications. Despite previous approaches [1], [2], accelerating spatial GNN remains challenging due to its unbalanced computing flow, poor locality, high sparsity, and high memory bandwidth requirements, especially for edge applications such as real-time motion detectors and point cloud processing. This work presents the first GNN computing-...Show More

A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce

Yipeng Wang;Shanshan Xie;Jacob Rohan;Meizhi Wang;Mengtian Yang;Sirish Oruganti;Jaydeep P. Kulkarni

2023 IEEE Custom Integrated Circuits Conference (CICC)

Year: 2023 | Conference Paper |

29.2 Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems

Shanshan Xie;Mengtian Yang;S. Andrew Lanham;Yipeng Wang;Meizhi Wang;Sirish Oruganti;Jaydeep P. Kulkarni

2023 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2023 | Conference Paper |

Cited by: Papers (7)

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Boolean satisfiability (SAT) is a non-deterministic polynomial time (NP)-complete problem with many practical and industrial data-intensive applications [1]. Examples (Fig. 29.2.1) include anti-aircraft mission planning in defense, gene prediction in vaccine development, network routing in the data center, automatic test pattern generation in electronic design automation (EDA), and model checking ...Show More

29.2 Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems

Shanshan Xie;Mengtian Yang;S. Andrew Lanham;Yipeng Wang;Meizhi Wang;Sirish Oruganti;Jaydeep P. Kulkarni

2023 IEEE International Solid-State Circuits Conference (ISSCC)

Year: 2023 | Conference Paper |

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Xiangxing Yang;Keren Zhu;Xiyuan Tang;Meizhi Wang;Mingtao Zhan;Nanshu Lu;Jaydeep P. Kulkarni;David Z. Pan;Yongpan Liu;Nan Sun

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 5 | Journal Article |

Cited by: Papers (8)

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The article presents a charge-domain computing ternary neural network (TNN) classifier with a complete four-layer neural network (NN) on a chip. The proposed ternary network provides 1.5-b resolution (0/+1/−1) for weights and activations, leading to 3.9× fewer operations (OPs) per inference than binary neural network (BNN) for the same Modified National Institute of Standards and Technology (MNIST...Show More

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

Xiangxing Yang;Keren Zhu;Xiyuan Tang;Meizhi Wang;Mingtao Zhan;Nanshu Lu;Jaydeep P. Kulkarni;David Z. Pan;Yongpan Liu;Nan Sun

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 5 | Journal Article |

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

Rishabh Sehgal;Tanmay Thareja;Shanshan Xie;Can Ni;Jaydeep P. Kulkarni

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 7 | Journal Article |

Cited by: Papers (10)

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The major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) that contribute to ~15% area and ~50% energy of the overall macro and are susceptible to non-linearities, leakage, and process variations, which causes deep neural network (DNN) inference/tr...Show More

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

Rishabh Sehgal;Tanmay Thareja;Shanshan Xie;Can Ni;Jaydeep P. Kulkarni

IEEE Journal of Solid-State Circuits

Year: 2023 | Volume: 58, Issue: 7 | Journal Article |

A High-Output Power 1-V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

Stafford Hutchins;Atresh Sanne;Zhanping Chen;Mohammad M. Hasan;Uddalak Bhattacharya;Eric Karl;Jaydeep P. Kulkarni

IEEE Solid-State Circuits Letters

Year: 2023 | Volume: 6 | Journal Article |

Cited by: Papers (1)

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A flexible, low-cost design solution for in-field-programmable (IFP) metal eFuse is reported. The design maximizes fuse yield through a tunable program voltage provided by a two-stage charge pump (CP), placed in closed loop (CL) with a low dropout regulator (LDO). The integration of CP and LDO solves electrical over-stress (EOS) concerns and achieves stability and low voltage operation through sev...Show More

A High-Output Power 1-V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

Stafford Hutchins;Atresh Sanne;Zhanping Chen;Mohammad M. Hasan;Uddalak Bhattacharya;Eric Karl;Jaydeep P. Kulkarni

IEEE Solid-State Circuits Letters

Year: 2023 | Volume: 6 | Journal Article |

Aging Effects On Clock Gated Memory Phase Paths

Amlan Ghosh;Saroj Satapathy;Jaydeep P. Kulkarni;Prashant D. Joshi

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Year: 2022 | Conference Paper |

Cited by: Papers (1)

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Transistor aging is a critical reliability issue affecting all nanoscale designs in advanced CMOS technologies. The aging affects the electrical properties of the transistors over time, degrading its performance depending on the amount of aging stress. In this work, we have specifically addressed the issue of clock duty cycle modulation in gated clock decoding paths due to asymmetric aging effects...Show More

Aging Effects On Clock Gated Memory Phase Paths

Amlan Ghosh;Saroj Satapathy;Jaydeep P. Kulkarni;Prashant D. Joshi

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Year: 2022 | Conference Paper |

Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM

Rahul Mathur;Mudit Bhargava;Heath Perry;Alberto Cestero;Frank Frederick;Daniel Smith;Daniel Fisher;Norman Robson;Brian Cline;Jaydeep. P. Kulkarni

IEEE Transactions on Electron Devices

Year: 2022 | Volume: 69, Issue: 12 | Journal Article |

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Traditional 2-D SRAM scaling has been slowing down and suffers from high parasitic resistance of critical signals like wordline (WL) and bitline (BL). As 3-D technologies such as hybrid wafer bonding (HWB) mature, increasingly finer pitches of 3-D interconnects are possible, enabling the possibility of 3-D partitioned memory designs. 3-D-split SRAMs, realized by splitting or folding an SRAM macro ...Show More

Early Design/Technology Exploration of BEOL Options for Hybrid Wafer Bonded Split-SRAM

Rahul Mathur;Mudit Bhargava;Heath Perry;Alberto Cestero;Frank Frederick;Daniel Smith;Daniel Fisher;Norman Robson;Brian Cline;Jaydeep. P. Kulkarni

IEEE Transactions on Electron Devices

Year: 2022 | Volume: 69, Issue: 12 | Journal Article |

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