Aarti Amod Agarkar - IEEE Xplore Author Profile

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Author details

Aarti Amod Agarkar

Also published under: Aarti Agarkar

Publications

6

Citations

15

Publications by Year

20162025

Co-Authors:

Himanshu AgrawalAtharva DhakateSuvidha DhakneShriram DindoreKalyani Ghuge

Show All Co-Authors (17)

Aarti Amod Agarkar

Also published under: Aarti Agarkar

Affiliation

Computer Engineering Department

Vishwakarma Institute of Technology

Pune, India

Publication Topics

Machine Learning,
Support Vector Machine,
Decision Tree,
Random Forest,
AdaBoost,
Additional Protocol,
Advances In Natural Language Processing,
Application Programming Interface,
Artificial Intelligence,
Artificial Intelligence Computing,
Artificial Neural Network,
Brand Name

Biography

Aarti Agarkar received her Bachelor of Engineering in Computer Science and Engineering from Walch and College of Engineering, Sangli, Maha-rashtra, India in 2001. She completed her Master of Engineering in Computer Science and Engineering from Savitribai Phule Pune University, Pune, Maha-rashtra, India in 2009. She had attended Symbiosis International University, Pune, Maharashtra, India and completed her PhD in 2019. Since 2002, she has been working as an academician. During the past 21 years. she served in academics holding different positions in India. She is currently associated with Marathawada Mitra Mandal's College of Engineering, Pune, India as an Associate Professor since January 2021. She has the responsibility of IQAC Coordinator...

Publications

6

Citations

15

Publications by Year

20162025

Co-Authors:

Himanshu Agrawal
Atharva Dhakate
Suvidha Dhakne
Shriram Dindore
Kalyani Ghuge

Show All Co-Authors (17)

Author's Published Works

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Showing 1-25 of 72 results

Conferences (51)

Journals (21)

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J.H. Lau(46)
J. Lau(26)
C. Chang(15)
S.-W.R. Lee(10)
D. Rice(6)
Express Packaging Systems, Inc., Palo Alto, CA, USA(23)
Hewlett Packard Company, Palo Alto, CA, USA(15)
Agilent Technologies, Inc., Santa Clara, CA, USA(9)
Agilent Technologies, Inc., San Jose, CA, USA(4)
Department of Mechanical Engineering, Hong Kong University of Science and Technology, Hong Kong, China(4)
IEEE Transactions on Components, Hybrids, and Manufacturing Technology(8)
IEEE Transactions on Electronics Packaging Manufacturing(6)
53rd Electronic Components and Technology Conference, 2003. Proceedings.(3)
IEEE Transactions on Components and Packaging Technologies(3)
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B(3)
IEEE(72)
Las Vegas, NV, USA(7)
San Diego, CA, USA(7)
Austin, TX, USA(4)
Hong Kong, China(3)
La Jolla, CA, USA(3)
Solder Joints(49)
Printed Circuit Board(48)
Thermal Expansion(41)
Young’s Modulus(30)
Finite Element(28)

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Results

Isothermal fatigue tests of plastic ball grid array (PBGA) SnAgCu lead-free solder joints at 60/spl deg/C

J. Lau;S.W.R. Lee;Fubin Song;D. Lau;Dongkai Shangguan

56th Electronic Components and Technology Conference 2006

Year: 2006 | Conference Paper |

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A new thermal-fatigue life prediction equation for a plastic ball grid array (PBGA) package with 95.5wt%Sn4.0wt%Ag0.5wt%Cu lead-free solder balls is proposed in this investigation. The test vehicle consists of the PBGA package, a lead-free PCB, and a lead-free solder paste (95.5wt%Sn3.9wt%Ag0.6wt%Cu). The coefficients of the fatigue equation presented herein are determined by best fit of the test ...Show More

Isothermal fatigue tests of plastic ball grid array (PBGA) SnAgCu lead-free solder joints at 60/spl deg/C

J. Lau;S.W.R. Lee;Fubin Song;D. Lau;Dongkai Shangguan

56th Electronic Components and Technology Conference 2006

Year: 2006 | Conference Paper |

Thermal stress analysis of a flip-chip parallel VCSEL (vertical-cavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints

J. Lau;W. Dauksher

56th Electronic Components and Technology Conference 2006

Year: 2006 | Conference Paper |

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Solders such as the 48wt%Sn-52wt%In, 42wt%Sn-58wt%Bi, 63wt%Sn-37wt%Pb, Sn(3-4)wt%Ag(0.5-0.7)wt%Cu, and 80wt%Au-20wt%Sn, are studied as interconnect materials in a vertical-cavity surface-emitting laser (VCSEL). The Sn52In alloy is a low temperature (melting point = 118degC) lead-free solder and a potential candidate material for this device. In this study, thermal-structural analysis evaluates the...Show More

Thermal stress analysis of a flip-chip parallel VCSEL (vertical-cavity surface-emitting laser) package with low-temperature lead-free (48Sn-52In) solder joints

J. Lau;W. Dauksher

56th Electronic Components and Technology Conference 2006

Year: 2006 | Conference Paper |

Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints

J. Lau;W. Dauksher

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Year: 2005 | Conference Paper |

Cited by: Papers (13)

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First Page of the Article

Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints

J. Lau;W. Dauksher

Proceedings Electronic Components and Technology, 2005. ECTC '05.

Year: 2005 | Conference Paper |

Thermal-fatigue life prediction equation for wafer-level chip scale package (WLCSP) lead-free solder joints on lead-free printed circuit board (PCB)

J.H. Lau;Dongkai Shangguan;D.C.Y. Lau;T.T.W. Kung;S.W.R. Lee

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

Year: 2004 | Conference Paper |

Cited by: Papers (6)

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A new thermal-fatigue life prediction equation for a class of lead-free solder alloys, 95.5wt%Sn3.9-4.0wt%Ag0.5-0.6wt%Cu is proposed in this investigation. The test vehicle consists of a lead-free solder-bumped WLCSP, lead-free PCB, and lead-free solder paste. The coefficients of the fatigue equation presented herein are determined by best fitted with the isothermal fatigue data of the test vehicl...Show More

Thermal-fatigue life prediction equation for wafer-level chip scale package (WLCSP) lead-free solder joints on lead-free printed circuit board (PCB)

J.H. Lau;Dongkai Shangguan;D.C.Y. Lau;T.T.W. Kung;S.W.R. Lee

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

Year: 2004 | Volume: 2 | Conference Paper |

Reliability testing and data analysis of an 1657CCGA (ceramic column grid array) package with lead-free solder paste on lead-free PCBs (printed circuit boards)

J. Lau;W. Dauksher;E. Ott;D. Shangguan;J. Smetana;R. Horsley;T. Castello;D. Love;I. Menis;B. Sullivan

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

Year: 2004 | Conference Paper |

Cited by: Papers (3)

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In this study, the thermal cycling test of the 1657CCGA package with 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb solder pastes on lead-free PCBs with HASL (hot-air solder leveling) CuSn, NiAu (electroless Ni and immersion Au, ENIG), and Entek OSP (organic solderability preservative) surface finishes are performed. The test stopped at 7500 cycles (0 to 100/spl deg/C, 40-minute cycle). The test dat...Show More

Reliability testing and data analysis of an 1657CCGA (ceramic column grid array) package with lead-free solder paste on lead-free PCBs (printed circuit boards)

J. Lau;W. Dauksher;E. Ott;D. Shangguan;J. Smetana;R. Horsley;T. Castello;D. Love;I. Menis;B. Sullivan

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

Year: 2004 | Volume: 1 | Conference Paper |

Acceleration models, constitutive equations, and reliability of lead-free solders and joints

J. Lau;W. Danksher;P. Vianco

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

Cited by: Papers (55)

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First Page of the Article

Acceleration models, constitutive equations, and reliability of lead-free solders and joints

J. Lau;W. Danksher;P. Vianco

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

3D large deformation and nonlinear stress analyses of tin whisker initiation and growth on lead-free components

J.H. Lau;S.H. Pan;Chen Xa

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

Cited by: Papers (4)

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First Page of the Article

3D large deformation and nonlinear stress analyses of tin whisker initiation and growth on lead-free components

J.H. Lau;S.H. Pan;Chen Xa

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

3D nonlinear thermal stress analysis of VCSEL (vertical-cavity surface-emitting laser) assemblies with lead-free flip-chip interconnects

Yida Zou;J. Lau;S. Catnerlo

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

Cited by: Papers (1)

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First Page of the Article

3D nonlinear thermal stress analysis of VCSEL (vertical-cavity surface-emitting laser) assemblies with lead-free flip-chip interconnects

Yida Zou;J. Lau;S. Catnerlo

53rd Electronic Components and Technology Conference, 2003. Proceedings.

Year: 2003 | Conference Paper |

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

J.H. Lau;C. Chang

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 3 | Journal Article |

Cited by: Papers (8)

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In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these under...Show More

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

J.H. Lau;C. Chang

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 3 | Journal Article |

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Cited by: Papers (20)

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Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia bu...Show More

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

J.H. Lau;S.-W.R. Lee

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Cited by: Papers (59)

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In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to ob...Show More

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

J.H. Lau;S.-W.R. Lee

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Effects of voids on bump chip carrier (BCC++) solder joint reliability

J. Lau;S. Erasmus;S. Pan

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)

Year: 2002 | Conference Paper |

Cited by: Papers (14)

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In this study, the effects of voids on the solder joint reliability of bump chip carrier (BCC++) packages on a printed circuit board are investigated. Emphasis is placed on the void size, void location, and void percentage. The solder is assumed to obey the Garofalo-Arrhenius creep constitutive equation. A total of 12 different cases are studied. In addition, the effects of voids on the crack grow...Show More

Effects of voids on bump chip carrier (BCC++) solder joint reliability

J. Lau;S. Erasmus;S. Pan

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)

Year: 2002 | Conference Paper |

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

IEEE Transactions on Components and Packaging Technologies

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Cited by: Papers (43)

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The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow...Show More

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

IEEE Transactions on Components and Packaging Technologies

Year: 2002 | Volume: 25, Issue: 1 | Journal Article |

Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

Year: 2001 | Conference Paper |

Cited by: Papers (1)

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The effect of a 2-layer microvia build-up printed circuit board (PCB) on the solder joint reliability of a wafer level chip scale package (WLCSP) assembly subject to thermal cycling is investigated in this study. The 62Sn-2Ag-36Pb solder joints are assumed to be: (1) an elastic material; (2) an elastic-plastic material; and (3) a creep material described by the Garofalo-Arrhenius creep constitutiv...Show More

Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220)

Year: 2001 | Conference Paper |

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

J.H. Lau;C. Chang;S.-W.R. Lee

IEEE Transactions on Components and Packaging Technologies

Year: 2001 | Volume: 24, Issue: 2 | Journal Article |

Cited by: Papers (28)

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The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mec...Show More

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

J.H. Lau;C. Chang;S.-W.R. Lee

IEEE Transactions on Components and Packaging Technologies

Year: 2001 | Volume: 24, Issue: 2 | Journal Article |

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

J.H. Lau;C. Chang

Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)

Year: 2000 | Conference Paper |

Cited by: Papers (3)

In this study, the fast-flow, fast-cure, and reworkable underfill materials from two different vendors are considered. Emphasis is placed on the determination of the curing conditions such as temperature and time, and the material properties such as the thermal coefficient of expansion (TCE), storage modulus, loss modulus, glass transition temperature (T/sub g/), and moisture uptake of these under...Show More

Characteristics and reliability of fast-flow, snap-cure, and reworkable underfills for solder bumped flip chip on low-cost substrates

J.H. Lau;C. Chang

Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)

Year: 2000 | Conference Paper |

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)

Year: 2000 | Conference Paper |

Cited by: Papers (9) | Patents (1)

Some of the critical issues of wafer level chip scale package (WLCSP) are discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layers o...

First Page of the Article

Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146)

Year: 2000 | Conference Paper |

Reliability of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag lead-free solder joints on build-up microvia printed circuit board

J.H. Lau;S.-W.R. Lee

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Cited by: Papers (1)

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale packages (WLCSP) on microvia build-up printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5 wt.%Sn-3.5 wt.%Ag. The 62 wt.%Sn-36 wt.%Pb-2 wt.%Ag solder is also considered to establish a baseline. These two sold...Show More

Reliability of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag lead-free solder joints on build-up microvia printed circuit board

J.H. Lau;S.-W.R. Lee

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Creep analysis of solder bumped direct chip attach (DCA) on microvia build-up printed circuit board with underfill

J.H. Lau;S.H. Pan;C. Chang

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Cited by: Papers (3)

The creep analysis of solder-bumped flip-chip on microvia build-up printed circuit board (PCB) with underfill encapsulant subjected to thermal cycling conditions are presented. Emphasis is placed on the effects of the conventional PCB's additional microvia build-up circuits on the solder joint reliability of the direct chip attach (DCA) assembly. The 62Sn-36Pb-2Ag solder joints are assumed to obey...Show More

Creep analysis of solder bumped direct chip attach (DCA) on microvia build-up printed circuit board with underfill

J.H. Lau;S.H. Pan;C. Chang

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Cited by: Papers (9)

The creep analyses of solder-bumped wafer level chip scale packages (WLCSP) on build-up printed circuit boards (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the conventional PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are as...Show More

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

J.H. Lau;S.-W.R. Lee

International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)

Year: 2000 | Conference Paper |

Taguchi design of experiment for wafer bumping by stencil printing

J.H. Lau;C. Chang

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2000 | Volume: 23, Issue: 3 | Journal Article |

Cited by: Papers (15)

Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8 in) wafer by the stencil printing method. These factors are: paste types, squeeze forces, snap-off heights, aperture shapes, and aspect ratios. They are varied to form a two-level L8 orthogonal array experiment. Analysis of mean (ANOM) and analysis of variance (ANOVA) are us...Show More

Taguchi design of experiment for wafer bumping by stencil printing

J.H. Lau;C. Chang

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2000 | Volume: 23, Issue: 3 | Journal Article |

Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants

J.H. Lau;S.-W.R. Lee;C. Chang

IEEE Transactions on Components and Packaging Technologies

Year: 2000 | Volume: 23, Issue: 2 | Journal Article |

Cited by: Papers (50) | Patents (1)

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five differe...Show More

Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants

J.H. Lau;S.-W.R. Lee;C. Chang

IEEE Transactions on Components and Packaging Technologies

Year: 2000 | Volume: 23, Issue: 2 | Journal Article |

Taguchi design of experiment for wafer bumping by stencil printing

J. Lau;C. Chang

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

Year: 2000 | Conference Paper |

Cited by: Papers (4)

Taguchi experiments are designed and carried out with five critical factors that influence the solder bumping of a 200 mm (8") wafer by stencil printing method. These factors are: paste types (type 3 and type 4), squeeze forces (9 and 12 lbs.), snap-off heights (0 and 5 mils), aperture shapes (square and circle), and aspect ratios (2.5 and 2.75). They are varied to form a two-level L8 orthogonal a...Show More

Taguchi design of experiment for wafer bumping by stencil printing

J. Lau;C. Chang

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

Year: 2000 | Conference Paper |

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

J. Lau;C. Chang;S.W.R. Lee

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

Year: 2000 | Conference Paper |

Cited by: Papers (16)

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mec...Show More

Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

J. Lau;C. Chang;S.W.R. Lee

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

Year: 2000 | Conference Paper |

Cost analysis: solder bumped flip chip versus wire bonding

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2000 | Volume: 23, Issue: 1 | Journal Article |

Cited by: Papers (25) | Patents (3)

The cost of wire bonding chips and solder bumped flip chips on boards or on organic substrates is studied. The effects of IC chip yields, gold and solder materials, and major equipment of these technologies on costs are examined. Useful equations and charts for determining the cost of and comparing the cost between these technologies are provided.Show More

Cost analysis: solder bumped flip chip versus wire bonding

IEEE Transactions on Electronics Packaging Manufacturing

Year: 2000 | Volume: 23, Issue: 1 | Journal Article |

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