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Janardhan Rao Doppa - IEEE Xplore Author Profile

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Author details

Janardhan Rao Doppa

Also published under: Jana Doppa

Publications

65

Citations

768

Publications by Year

20132025

Co-Authors:

Raid AyoubKanad BasuSyrine BelakariaTaha BelkhoujaGanapati Bhat

Show All Co-Authors (80)

Janardhan Rao Doppa

Also published under: Jana Doppa

Affiliation

Department of Electrical Engineering and Computer Science

Washington State University

Pullman, WA, USA

Publication Topics

Resistive Random Access Memory,
Convolutional Neural Network,
Accuracy Loss,
Area Overhead,
CIFAR-100 Dataset,
Deep Neural Network,
Accuracy Drop,
Convolutional Neural Network Training,
Crossbar Array,
Neural Network,
Pruning Method,
Convolutional Neural Network Model

Biography

Janardhan Rao Doppa (Senior Member, IEEE) received the Ph.D. degree in computer science from Oregon State University, Corvallis, OR, USA.,He is the Huie-Rogers Endowed Chair Associate Professor with Washington State University,Pullman, WA, USA. His research interests are the intersection of machine learning and computing systems design.,Dr. Doppa won the NSF CAREER Award, the Outstanding Paper Award from AAAI Conference in 2013, the Best Paper Award from ACM Transactions on Design Automation of Electronic Systems in 2021, the IJCAI Early Career Award in 2021, the Best Paper Award from Embedded Systems Week Conference in 2022 and 2023, the Best Paper Award from International Symposium on Low-Power Electronic Design in 2023, the Outstanding J...

Publications

65

Citations

768

Publications by Year

20132025

Co-Authors:

Raid Ayoub
Kanad Basu
Syrine Belakaria
Taha Belkhouja
Ganapati Bhat

Show All Co-Authors (80)

Author's Published Works

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Showing 1-25 of 65 results

Conferences (37)

Journals (23)

Magazines (3)

Early Access Articles (2)

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Janardhan Rao Doppa(64)
Partha Pratim Pande(51)
Krishnendu Chakrabarty(25)
Biresh Kumar Joardar(24)
Ryan Gary Kim(10)
School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA(12)
School of EECS, Washington State University, Pullman, WA, USA(11)
Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA(11)
Department of ECE, Duke University, Durham, NC, USA(10)
School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA(6)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(14)
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)(4)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems(4)
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)(3)
2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)(3)
IEEE(65)
Media(2)
Grenoble, France(5)
San Diego, CA, USA(5)
Munich, Germany(4)
Antwerp, Belgium(3)
Seoul, Korea (South)(3)
Resistive Random Access Memory(25)
Convolutional Neural Network(20)
Deep Neural Network(17)
3D Architecture(15)
Design Space(15)

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Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures

Pratyush Dhingra;Janardhan Rao Doppa;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2025 | Early Access Article |

Transformer architectures have become the standard neural network model for various machine learning applications including natural language processing and computer vision. However, the compute and memory requirements introduced by transformer models make them challenging to adopt for edge applications. Furthermore, fine-tuning pre-trained transformers (e.g., foundation models) is a common task to...Show More

Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures

Pratyush Dhingra;Janardhan Rao Doppa;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2025 | Early Access Article |

Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units

Gaurav Narang;Janardhan Rao Doppa;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Early Access Article |

Operation Unit (OU)-based configurations enable the design of energy-efficient and reliable ReRAM crossbar-based Processing-In-Memory (PIM) architectures for Deep Neural Network (DNN) inferencing. To exploit sparsity and tackle crossbar non-idealities, matrix-vector-multiplication (MVM) operations are computed at a much smaller level of granularity than a full crossbar, referred to as OUs. However...Show More

Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units

Gaurav Narang;Janardhan Rao Doppa;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Early Access Article |

HuNT: Exploiting Heterogeneous PIM Devices to Design a 3-D Manycore Architecture for DNN Training

Chukwufumnanya Ogbogu;Gaurav Narang;Biresh Kumar Joardar;Janardhan Rao Doppa;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 11 | Journal Article |

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Processing-in-memory (PIM) architectures have emerged as an attractive computing paradigm for accelerating deep neural network (DNN) training and inferencing. However, a plethora of PIM devices, e.g., resistive random-access memory, ferroelectric field-effect transistor, phase change memory, MRAM, static random-access memory, exists and each of these devices offers advantages and drawbacks in term...Show More

HuNT: Exploiting Heterogeneous PIM Devices to Design a 3-D Manycore Architecture for DNN Training

Chukwufumnanya Ogbogu;Gaurav Narang;Biresh Kumar Joardar;Janardhan Rao Doppa;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 11 | Journal Article |

Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN Accelerators

Xueying Wu;Edward Hanson;Nansu Wang;Qilin Zheng;Xiaoxuan Yang;Huanrui Yang;Shiyu Li;Feng Cheng;Partha Pratim Pande;Janardhan Rao Doppa;Krishnendu Chakrabarty;Hai Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 12 | Journal Article |

Cited by: Papers (1)

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Resistive random access memory (ReRAM)-based processing-in-memory (PIM) architectures have demonstrated great potential to accelerate the deep neural network (DNN) training/inference. However, the computational accuracy of analog PIM is compromised due to the nonidealities, such as the conductance variation of ReRAM cells. The impact of these nonidealities worsens as the number of concurrently act...Show More

Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN Accelerators

Xueying Wu;Edward Hanson;Nansu Wang;Qilin Zheng;Xiaoxuan Yang;Huanrui Yang;Shiyu Li;Feng Cheng;Partha Pratim Pande;Janardhan Rao Doppa;Krishnendu Chakrabarty;Hai Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 12 | Journal Article |

Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks

Ching-Yuan Chen;Biresh Kumar Joardar;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 8 | Journal Article |

Cited by: Papers (1)

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Graph neural networks (GNNs) are becoming popular in various real-world applications. However, hardware-level security is a concern when GNN models are mapped to emerging neuromorphic computing architectures, such as memristor-based crossbars. We identify a vulnerability of memristor-mapped GNNs and propose an attack mechanism based on the identified vulnerability. The proposed attack tampers memr...Show More

Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks

Ching-Yuan Chen;Biresh Kumar Joardar;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2024 | Volume: 43, Issue: 8 | Journal Article |

Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems

Gaurav Narang;Raid Ayoub;Michael Kishinevsky;Janardhan Rao Doppa;Partha Pratim Pande

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

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Large-scale manycore System-on-Chips (SoCs) need to satisfy the conflicting objectives of maximizing performance and minimizing energy consumption for dynamically changing applications. In this paper, we consider the problem of dynamic power management (DPM) in large manycore SoCs for unseen applications at runtime. We employ a machine learning (ML) based DPM policy, which selects the voltage/freq...Show More

Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems

Gaurav Narang;Raid Ayoub;Michael Kishinevsky;Janardhan Rao Doppa;Partha Pratim Pande

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC

Chukwufumnanya Ogbogu;Mohapatra Soumen;Biresh Kumar Joardar;Janardhan Rao Doppa;Deuk Heo;Krishnendu Chakrabarty;Partha Pratim Pande

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

Cited by: Papers (2)

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Machine learning (ML) models have gained prominence in solving real-world tasks. However, implementing ML models is both compute- and memory-intensive. Domain-specific architectures such as Resistive Random Access Memory (ReRAM)-based Processing-in-Memory (PIM) platforms have been proposed to efficiently accelerate ML training and inference. However, existing ML workloads require a high amount of ...Show More

Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC

Chukwufumnanya Ogbogu;Mohapatra Soumen;Biresh Kumar Joardar;Janardhan Rao Doppa;Deuk Heo;Krishnendu Chakrabarty;Partha Pratim Pande

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

Energy-Efficient Missing Data Recovery in Wearable Devices: A Novel Search-Based Approach

Dina Hussein;Taha Belkhouja;Ganapati Bhat;Janardhan Rao Doppa

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

Cited by: Papers (2)

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Wearable and internet of things (IoT) devices are transforming a number of high-impact applications. Machine learning (ML) algorithms on wearable devices assume that data from all sensors is available at runtime. However, one or more sensors may be unavailable at runtime due to malfunction, energy constraints or communication challenges. Loss of sensor data can potentially lead to severe degradati...Show More

Energy-Efficient Missing Data Recovery in Wearable Devices: A Novel Search-Based Approach

Dina Hussein;Taha Belkhouja;Ganapati Bhat;Janardhan Rao Doppa

2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Year: 2023 | Conference Paper |

CALDA: Improving Multi-Source Time Series Domain Adaptation With Contrastive Adversarial Learning

Garrett Wilson;Janardhan Rao Doppa;Diane J. Cook

IEEE Transactions on Pattern Analysis and Machine Intelligence

Year: 2023 | Volume: 45, Issue: 12 | Journal Article |

Cited by: Papers (11)

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Unsupervised domain adaptation (UDA) provides a strategy for improving machine learning performance in data-rich (target) domains where ground truth labels are inaccessible but can be found in related (source) domains. In cases where meta-domain information such as label distributions is available, weak supervision can further boost performance. We propose a novel framework, CALDA, to tackle these...Show More

CALDA: Improving Multi-Source Time Series Domain Adaptation With Contrastive Adversarial Learning

Garrett Wilson;Janardhan Rao Doppa;Diane J. Cook

IEEE Transactions on Pattern Analysis and Machine Intelligence

Year: 2023 | Volume: 45, Issue: 12 | Journal Article |

Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars

Chung-Hsuan Tung;Biresh Kumar Joardar;Partha Pratim Pande;Janardhan Rao Doppa;Hai Helen Li;Krishnendu Chakrabarty

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2023 | Conference Paper |

Cited by: Papers (5)

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A ReRAM crossbar-based computing system (RCS) can accelerate CNN training. However, hardware faults due to manufacturing defects and limited endurance impede the widespread adoption of RCS. We propose a dynamic task remapping-based technique for reliable CNN training on faulty RCS. Experimental results demonstrate that the proposed low-overhead method incurs only 0.85% accuracy loss on average whi...Show More

Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars

Chung-Hsuan Tung;Biresh Kumar Joardar;Partha Pratim Pande;Janardhan Rao Doppa;Hai Helen Li;Krishnendu Chakrabarty

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2023 | Conference Paper |

Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures

Harsh Sharma;Sumit K. Mandal;Janardhan Rao Doppa;Umit Ogras;Partha Pratim Pande

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2023 | Conference Paper |

Cited by: Papers (4)

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Chiplet-based 2.5D systems that integrate multiple smaller chips on a single die are gaining popularity for executing both compute-and data-intensive applications. While smaller chips (chiplets) reduce fabrication costs, they also provide less functionality. Hence, manufacturing several smaller chiplets and combining them into a single system enables the functionality of a larger monolithic chip w...Show More

Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures

Harsh Sharma;Sumit K. Mandal;Janardhan Rao Doppa;Umit Ogras;Partha Pratim Pande

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2023 | Conference Paper |

Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning

Chukwufumnanya O. Ogbogu;Aqeeb Iqbal Arka;Lukas Pfromm;Biresh Kumar Joardar;Janardhan Rao Doppa;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 8 | Journal Article |

Cited by: Papers (5)

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Graph neural networks (GNNs) are used for predictive analytics on graph-structured data, and they have become very popular in diverse real-world applications. Resistive random-access memory (ReRAM)-based PIM architectures can accelerate GNN training. However, GNN training on ReRAM-based architectures is both compute- and data intensive in nature. In this work, we propose a framework called SlimGNN...Show More

Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning

Chukwufumnanya O. Ogbogu;Aqeeb Iqbal Arka;Lukas Pfromm;Biresh Kumar Joardar;Janardhan Rao Doppa;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 8 | Journal Article |

Dynamic Time Warping Based Adversarial Framework for Time-Series Domain

Taha Belkhouja;Yan Yan;Janardhan Rao Doppa

IEEE Transactions on Pattern Analysis and Machine Intelligence

Year: 2023 | Volume: 45, Issue: 6 | Journal Article |

Cited by: Papers (15)

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Despite the rapid progress on research in adversarial robustness of deep neural networks (DNNs), there is little principled work for the time-series domain. Since time-series data arises in diverse applications including mobile health, finance, and smart grid, it is important to verify and improve the robustness of DNNs for the time-series domain. In this paper, we propose a novel framework for th...Show More

Dynamic Time Warping Based Adversarial Framework for Time-Series Domain

Taha Belkhouja;Yan Yan;Janardhan Rao Doppa

IEEE Transactions on Pattern Analysis and Machine Intelligence

Year: 2023 | Volume: 45, Issue: 6 | Journal Article |

ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs

Biresh Kumar Joardar;Janardhan Rao Doppa;Hai Li;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Emerging Topics in Computing

Year: 2023 | Volume: 11, Issue: 2 | Journal Article |

Cited by: Papers (3)

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Training machine learning (ML) models at the edge (on-chip training on end user devices) can address many pressing challenges including data privacy/security, increase the accessibility of ML applications to different parts of the world by reducing the dependence on the communication fabric and the cloud infrastructure, and meet the real-time requirements of AR/VR applications. However, existing e...Show More

ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs

Biresh Kumar Joardar;Janardhan Rao Doppa;Hai Li;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Emerging Topics in Computing

Year: 2023 | Volume: 11, Issue: 2 | Journal Article |

ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems

Xiaoxuan Yang;Huanrui Yang;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabartys;Hai Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 7 | Journal Article |

Cited by: Papers (4)

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Processing-in-memory (PIM) enables energy-efficient deployment of convolutional neural networks (CNNs) from edge to cloud. Resistive random-access memory (ReRAM) is one of the most commonly used technologies for PIM architectures. One of the primary limitations of ReRAM-based PIM in neural network training arises from the limited write endurance due to the frequent weight updates. To make ReRAM-ba...Show More

ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems

Xiaoxuan Yang;Huanrui Yang;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabartys;Hai Li

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2023 | Volume: 42, Issue: 7 | Journal Article |

Fault-tolerant Deep Learning using Regularization

Biresh Kumar Joardar;Aqeeb Iqbal Arka;Janardhan Rao Doppa;Partha Pratim Pande

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

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Resistive random-access memory has become one of the most popular choices of hardware implementation for machine learning application workloads. However, these devices exhibit non-ideal behavior, which presents a challenge towards widespread adoption. Training/inferencing on these faulty devices can lead to poor prediction accuracy. However, existing fault tolerant methods are associated with high...Show More

Fault-tolerant Deep Learning using Regularization

Biresh Kumar Joardar;Aqeeb Iqbal Arka;Janardhan Rao Doppa;Partha Pratim Pande

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

Reliable Machine Learning for Wearable Activity Monitoring: Novel Algorithms and Theoretical Guarantees

Dina Hussein;Taha Belkhouja;Ganapati Bhat;Janardhan Rao Doppa

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

Cited by: Papers (2)

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Wearable devices are becoming popular for health and activity monitoring. The machine learning (ML) models for these applications are trained by collecting data in a laboratory with precise control of experimental settings. However, during real-world deployment/usage, the experimental settings (e.g., sensor position or sampling rate) may deviate from those used during training. This discrepancy ca...Show More

Reliable Machine Learning for Wearable Activity Monitoring: Novel Algorithms and Theoretical Guarantees

Dina Hussein;Taha Belkhouja;Ganapati Bhat;Janardhan Rao Doppa

2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2022 | Conference Paper |

SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator

Harsh Sharma;Sumit K. Mandal;Janardhan Rao Doppa;Umit Y. Ogras;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

Cited by: Papers (12)

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Processing-in-memory (PIM) is a promising technique to accelerate deep learning (DL) workloads. Emerging DL workloads (e.g., ResNet with 152 layers) consist of millions of parameters, which increase the area and fabrication cost of monolithic PIM accelerators. The fabrication cost challenge can be addressed by 2.5-D systems integrating multiple PIM chiplets connected through a network-on-package (...Show More

SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator

Harsh Sharma;Sumit K. Mandal;Janardhan Rao Doppa;Umit Y. Ogras;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet

Chukwufumnanya Ogbogu;Aqeeb Iqbal Arka;Biresh Kumar Joardar;Janardhan Rao Doppa;Hai Li;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

Cited by: Papers (8)

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Resistive random-access memory (ReRAM)-based manycore architectures enable acceleration of graph neural network (GNN) inference and training. GNNs exhibit characteristics of both DNNs and graph analytics. Hence, GNN training/inferencing on ReRAM-based manycore architectures give rise to both computation and on-chip communication challenges. In this work, we leverage model pruning and efficient gra...Show More

Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet

Chukwufumnanya Ogbogu;Aqeeb Iqbal Arka;Biresh Kumar Joardar;Janardhan Rao Doppa;Hai Li;Krishnendu Chakrabarty;Partha Pratim Pande

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 11 | Journal Article |

DIET: A Dynamic Energy Management Approach for Wearable Health Monitoring Devices

Nuzhat Yamin;Ganapati Bhat;Janardhan Rao Doppa

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2022 | Conference Paper |

Cited by: Papers (7)

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Wearable devices are becoming increasingly popular for health and activity monitoring applications. These devices typically include small rechargeable batteries to improve user comfort. However, the small battery capacity leads to limited operating life, requiring frequent recharging. Recent research has proposed energy harvesting using light and user motion to improve the lifetime of wearable dev...Show More

DIET: A Dynamic Energy Management Approach for Wearable Health Monitoring Devices

Nuzhat Yamin;Ganapati Bhat;Janardhan Rao Doppa

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2022 | Conference Paper |

Machine Learning Enabled Design Automation and Multi-Objective Optimization for Electric Transportation Power Systems

Derek Jackson;Syrine Belakaria;Yue Cao;Janardhan Rao Doppa;Xiaonan Lu

IEEE Transactions on Transportation Electrification

Year: 2022 | Volume: 8, Issue: 1 | Journal Article |

Cited by: Papers (4)

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This article presents an automated design and optimization framework for electric transportation power systems (ETPS) enabled by machine learning (ML). The use of physical models, simulations, and optimization methods can greatly aid the engineering design process. However, when considering the optimal co-design of multiple interdependent subsystems that span multiple physical domains, such model-...Show More

Machine Learning Enabled Design Automation and Multi-Objective Optimization for Electric Transportation Power Systems

Derek Jackson;Syrine Belakaria;Yue Cao;Janardhan Rao Doppa;Xiaonan Lu

IEEE Transactions on Transportation Electrification

Year: 2022 | Volume: 8, Issue: 1 | Journal Article |

High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers

Biresh Kumar Joardar;Aryan Deshwal;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 5 | Journal Article |

Cited by: Papers (7)

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Resistive random-access memory (ReRAM)-based architectures can be used to accelerate convolutional neural network (CNN) training. However, existing architectures either do not support normalization at all or they support only a limited version of it. Moreover, it is common practice for CNNs to add normalization layers after every convolution layer. In this work, we show that while normalization la...Show More

High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers

Biresh Kumar Joardar;Aryan Deshwal;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2022 | Volume: 41, Issue: 5 | Journal Article |

Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise

Xiaoxuan Yang;Syrine Belakaria;Biresh Kumar Joardar;Huanrui Yang;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty;Hai Helen Li

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

Cited by: Papers (25)

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Resistive random-access memory (ReRAM) is a promising technology for designing hardware accelerators for deep neural network (DNN) inferencing. However, stochastic noise in ReRAM crossbars can degrade the DNN inferencing accuracy. We propose the design and optimization of a high-performance, area-and energy-efficient ReRAM-based hardware accelerator to achieve robust DNN inferencing in the presenc...Show More

Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise

Xiaoxuan Yang;Syrine Belakaria;Biresh Kumar Joardar;Huanrui Yang;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty;Hai Helen Li

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks

Aqeeb Iqbal Arka;Biresh Kumar Joardar;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

Cited by: Papers (10)

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Graph Neural Networks (GNNs) are a variant of Deep Neural Networks (DNNs) operating on graphs. GNNs have attributes of both DNNs and graph computation. However, training GNNs on manycore architectures is a challenging task because it involves heavy communication that bottlenecks performance. DropEdge and Dropout, which we collectively refer to as DropLayer, are regularization techniques that can i...Show More

DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks

Aqeeb Iqbal Arka;Biresh Kumar Joardar;Janardhan Rao Doppa;Partha Pratim Pande;Krishnendu Chakrabarty

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AI

Nitthilan Kannappan Jayakodi;Janardhan Rao Doppa;Partha Pratim Pande

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

Cited by: Papers (6)

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A huge number of edge applications including self-driving cars, mobile health, robotics, and augmented reality / virtual reality are enabled by deep neural networks (DNNs). Currently, much of this computation for these applications happens in the cloud, but there are several good reasons to perform the processing on local edge platforms such as smartphones: improved accessibility to different part...Show More

A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AI

Nitthilan Kannappan Jayakodi;Janardhan Rao Doppa;Partha Pratim Pande

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

Year: 2021 | Conference Paper |

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