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Edge Engineered Graphene Nanoribbons as Nanoscale Interconnect: DFT Analysis
Sonal Agrawal;Anurag Srivastava;Gaurav Kaushal;Ashok Srivastava
Density functional theory (DFT) with non-equilibrium Green's function (NEGF) formalism and HSPICE simulator have been used to analyse the effect of elemental oxygen atom passivation on the structural, electronic and transport properties of Graphene Nanoribbons (GNRs). The analysis of delay, power dissipation, crosstalk effect, stability and frequency analysis has also been performed to understand ...Show More
High Q-Factor Graphene-Based Inductor CMOS LC Voltage Controlled Oscillator for PLL Applications
Naheem Olakunle Adesina;Md Azmot Ullah Khan;Ashok Srivastava
2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
This work examines the design of high Q-factor inductor for LC voltage-controlled oscillator (VCO) in TSMC 0.18μm n-well CMOS process technology and 1.5 V supply voltage. The planar structure of graphene and its sufficient relation time make it easier to pattern graphene into helical structures without additional contacts at each corner. The inductor is modelled with the widely accepted π-mudel an...Show More
Phase Noise and Jitter Measurements in SEU-Hardened CMOS Phase Locked Loop Design
Naheem Olakunle Adesina;Ashok Srivastava;Md Azmot Ullah Khan;Jian Xu
2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS)
Year: 2021 | Conference Paper |
Cited by: Papers (8)
Single event upset (SEU) is a significant problem in analog, digital, and mixed signal circuits. The extent of the attacks increases in radiation susceptible environments such as military and aerospace. Phase locked loop (PLL) is ubiquitous and usually employed as data recovery or clock signal in some electronic devices used in these environments. Single event transient causes ionizing particles t...Show More
An Ultra-Low Power MOS2 Tunnel Field Effect Transistor PLL Design for IoT Applications
Naheem Olakunle Adesina;Ashok Srivastava;Azmot Ullah Khan;Jian Xu
2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS)
Year: 2021 | Conference Paper |
Cited by: Papers (7)
This work presents the implementation of analytical transport model of MoS2tunnel field effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model are extracted, and most notable is its high ION/IOFF ratio, which makes it suitable for low power design, and IoT applications. Subsequently, we employ the TFET model in the design of ultralow power phase locked loop (PLL)....Show More
Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design
Naheem Olakunle Adesina;Ashok Srivastava;Md Azmot Ullah Khan
2021 IEEE 11th Annual Computing and Communication Workshop and Conference (CCWC)
Year: 2021 | Conference Paper |
Cited by: Papers (15)
There are limitations in CMOS transistor as the technology scales down. The problem of short channel effects (SCE) has become dominant, which causes the malfunction and failure of CMOS circuits. Various devices are proposed to continue extending Moore's law and the roadmap in semiconductor industry. Memristor is a two terminal passive device, which has proven to be compatible with MOSFET microfabr...Show More
A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology
2020 11th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)
Year: 2020 | Conference Paper |
Cited by: Papers (13)
There are tremendous improvements in performance of transistor in CMOS technology by scaling down its size. However, there are various challenges, such as short channel effects (SCE), that are associated with miniaturization. FinFET technology is a promising technique to overcome these issues because it offers better electrostatic control of the channel than planar CMOS transistor as the technolog...Show More
Analytical Current Transport Modeling of Monolayer Molybdenum Disulfide-Based Dual Gate Tunnel Field Effect Transistor
Md Azmot Ullah Khan;Ashok Srivastava;Clay Mayberry;Ashwani K Sharma
In this paper, we present a current transport model of MoS2-based dual gate tunnel field effect transistor from both analytical and numerical techniques. In analytical modeling, two-dimensional (2D) model of potential distribution with its corresponding energy level for the hetero-junction has been solved and implemented with Landauer current transport mechanism. The output characteristics have be...Show More
Novel, Low-power ECRL-CMOS Interface Circuit
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2019 | Conference Paper |
Adiabatic logic families typically use signal waveforms very different to standard static CMOS logic. Pulsed power-clocks driving the circuit lead to pulsed or sinusoidal signals that cannot be easily interfaced with existing CMOS logic structures. This work focuses on a novel interface circuit that converts existing signals in ECRL (efficient charge recovery logic) to signals typical of standard ...Show More
Synthesis of Two-Dimensional Diamond From Graphene on Copper
2019 Electron Devices Technology and Manufacturing Conference (EDTM)
Year: 2019 | Conference Paper |
We report, for the first-time pressure-less synthesis of 2D diamond thin film from graphene on a copper foil using cold wall CVD. Continuous hydrogenation of multilayer graphene on a copper substrate results in stable phase transition of graphene to optically visible diamond thin film on the copper foil. Characteristic sp3 C-C bond in X-ray photoelectron spectroscopy and Raman characteristic diamo...Show More
Evaluation of Four Power Gating Schemes Applied to ECRL Adiabatic Logic
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
In this paper, four different power-clock gating schemes for use with four-phase adiabatic logic were evaluated and compared with respect to idle power reduction and active power consumption increase. Specifically, single buffer/inverter structures implemented in efficient charge recovery logic (ECRL) were used to generate the simulation data. Separate header and footer power-gating schemes were c...Show More
SPICE-Compatible Modeling of Silicene Field Effect Transistor and Analog Circuit Design
2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC)
Year: 2018 | Conference Paper |
We present review of the current transport behavior of silicene field effect transistor (FET) in which a monolayer of honeycomb lattice made of silicon is used as a transport channel. Based on this study, we introduce a SPICE-compatible model of the silicene FET. The proposed model is characterized by the channel dimension, temperature and externally applied voltage. In addition, vacancy defects i...Show More
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses
Shaoming Chen;Lu Peng;Samuel Irving;Zhou Zhao;Weihua Zhang;Ashok Srivastava
Multisocket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of intersocket communication especially for massive parallel workloads that generate many intersocket requests for synchronizations and remote memory accesses. Intersocket traffic puts pressure on the underlying network connecting all processors with a limited bandwidth conf...Show More
Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube Interconnects
Electrothermal performance of multiwall carbon nanotubes (MWCNT)-based interconnects has been studied under the influence of self-heating. The interlayer insulator is a low-k (εr ~ 2) dielectric. Various geometries have been studied for the normal operation and breakdown conditions. Electrothermal coupled equations have been solved iteratively by solving Fourier heat diffusion equation with a fini...Show More
Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design
Zhou Zhao;Xinlu Chen;Ashok Srivastava;Lu Peng;Saraju P. Mohanty
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Year: 2017 | Conference Paper |
Graphene barristor, in which a Schottky barrier formed between graphene layer and silicon layer can widen the bandgap with the control of gate voltage, is a promising method to enhance on/off current ratio in digital circuit design. In this work, a theoretical study is presented based on analog behavior modeling in SPICE. We have developed a compact device model to evaluate the performance of grap...Show More
Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors
Shaoming Chen;Samuel Irving;Lu Peng;Yue Hu;Ying Zhang;Ashok Srivastava
Off-chip memory bandwidth has been considered as one of the major limiting factors of processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observe that a processor requires much less power during memory intensive stages than i...Show More
Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency Applications
2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Year: 2016 | Conference Paper |
Cited by: Papers (1)
A numerical simulation based on self-consistent solution of non-equilibrium Green's function (NEGF) formulism and Poisson equation has been developed in order to investigate the width-dependent characteristics of GNR FETs in two GNR families (3p,0) and (3p+1,0). On-state characteristics such as transfer characteristics, transconductance, gate capacitance, intrinsic cut-off frequency and intrinsic ...Show More
Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design
2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Year: 2016 | Conference Paper |
Cited by: Papers (9)
Performance of graphene nanoribbon (GNR) tunnel field effect transistor (TFET) has been modeled in Verilog-Analog (Verilog-A) using previously reported physics based compact analytical current transport model. Performance obtained using both analytical model and Verilog-A simulations are compared providing excellent match. Using n-type and p-type GNR TFETs, inverter circuit is designed and simulat...Show More
Transport Phenomenon in Boron–GroupV Linear Atomic Chains Under Tensile Stress for Nanoscale Devices and Interconnects: First Principles Analysis
Boddepalli SanthiBhushan;Anurag Srivastava;Mohammad Shahzad Khan;Ashok Srivastava;Souraya Goumri-Said
Density functional theory and nonequilibrium Green's function-based first principle calculations have been performed for an in-depth analysis of infinitely long boron-groupV (N, P, As, and Sb) linear atomic chains (LACs) under tensile stress. The analysis revealed the presence of dative bond among the atoms of LAC, and loses stability of the structures with applied stress. The boron phosphide (BP)...Show More
A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Year: 2016 | Conference Paper |
Cited by: Papers (1)
Low power and robust circuitry are permanent hotspots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence pow...Show More
Analytical Current Transport Modeling of Graphene Nanoribbon Tunnel Field-Effect Transistors for Digital Circuit Design
Md Shamiul Fahad;Ashok Srivastava;Ashwani K. Sharma;Clay Mayberry
A semi-classical and a semi-quantum current transport model for p-i-n n-type armchair graphene nanoribbon tunnel field effect transistor (TFET) are studied analytically. The results are compared with the numerical quantum transport simulation method using an atomistic Schrodinger–Poisson solver within the non-equilibrium Green function (NEGF) formalism. The channel length and width are 20 and 4.9 ...Show More
Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors
2015 IEEE International Symposium on Nanoelectronic and Information Systems
Year: 2015 | Conference Paper |
In this paper, graphene nanoribbon field effect transistors (GNR FET) have been used in design of new energy-efficient XNOR/XOR gates based on clocked adiabatic logic (CAL), which results in the reduction of power density by nearly 65% comparing with the earlier CAL design in 45 nm technology node. In addition, the GNR FET allows scaling of supply voltage, which results in nearly three times reduc...Show More
Circuit Implementation of Switchable Pins in Chip Multiprocessor
Zhou Zhao;Ashok Srivastava;Lu Peng;Shaoming Chen;Saraju Mohanty
2015 IEEE International Symposium on Nanoelectronic and Information Systems
Year: 2015 | Conference Paper |
Cited by: Papers (1)
Transistor scaling and voltage scaling promote the development of VLSI chip design and modern portable devices. However, transistor scaling brings dark silicon to chips. Lowering supply voltage also results in many transistors to work in near threshold voltage region in which transistors are very sensitive to voltage variation. The paper analyzes the influence of IR drop in a chip multiprocessor (...Show More
An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip
2015 IEEE Computer Society Annual Symposium on VLSI
Year: 2015 | Conference Paper |
Cited by: Papers (1)
Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable t...Show More
Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching
Shaoming Chen;Lu Peng;Yue Hu;Zhou Zhao;Ashok Srivastava;Ying Zhang;Jin-Woo Choi;Bin Li;Edward Song
The end of Dennard scaling has led to a large amount of inactive or significantly underclocked transistors on modern chip multiprocessors in order to comply with the power budget and prevent the processors from overheating. This so-called dark silicon is one of the most critical constraints that will hinder the scaling with Moore's Law in future. While advanced cooling techniques, such as liquid c...Show More
Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology
In this paper, we have investigated the static metrics and switching attributes of graphene nanoribbon field-effect transistors (GNR FETs) for scaling the channel length from 15 nm down to 2.5 nm and GNR width by approaching the ultimate vertical scaling of oxide thickness. We have simulated the double-gate GNR FET by solving a numerical quantum transport model based on selfconsistent solution of ...Show More
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