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Kazutaka Kikuta - IEEE Xplore Author Profile

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Author details

Kazutaka Kikuta

Publications

21

Citations

148

Publications by Year

20132022

Co-Authors:

Iakov ChemyakGrigory ChernyakWeike FengHiroyuki FujitaZhengli Han

Show All Co-Authors (16)

Kazutaka Kikuta

Affiliation

Center for Northeast Asian Studies

Tohoku University

Sendai, Japan

Publication Topics

Synthetic Aperture Radar,
Phase Difference,
Absolute Velocity,
Arrival Time,
Atmospheric Parameters,
Atmospheric Phase,
Atmospheric Phase Screen,
Average Signal,
Azimuth Direction,
Bistable System,
Caldera,
Dielectric Constant

Biography

Kazutaka Kikuta (Member, IEEE) received the B.Eng., M.Eng., and Ph.D. degrees from The University of Tokyo, Tokyo, Japan, in 2012, 2014, and 2017, respectively.,Since 2017, he has been an Assistant Professor with the Center for Northeast Asian Studies, Tohoku University, Sendai, Japan. His research interests include signal processing of ground penetrating radar and ground-based synthetic aperture radar.,Dr. Kikuta is a member of IEICE.(Based on document published on 26 February 2020).

Publications

21

Citations

148

Publications by Year

20132022

Co-Authors:

Iakov Chemyak
Grigory Chernyak
Weike Feng
Hiroyuki Fujita
Zhengli Han

Show All Co-Authors (16)

Author's Published Works

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Showing 1-25 of 4,112 resultsfor "Index Terms":Double-gate

Conferences (3,009)

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Optimum crystallographic alignment for Si n-channel ballistic DGFETs

IEEE Electron Device Letters

Year: 2005 | Volume: 26, Issue: 9 | Journal Article |

Cited by: Papers (3)

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Optimum intrinsic device switching time for a 7.5-nm gate-length Si n-channel double-gate field-effect transistor (DGFET) in the limit of pure ballistic transport occurs when channel quantization/transport directions are aligned to the / crystallographic directions, respectively. The computed switching time of 0.123 ps is 5% less than the value obtained with the more "conventional" a...Show More

Optimum crystallographic alignment for Si n-channel ballistic DGFETs

IEEE Electron Device Letters

Year: 2005 | Volume: 26, Issue: 9 | Journal Article |

Full Subtractor Circuit Design with Independent Double Gate Transistor

Viranjay M. Srivastava;Shipra Kapoor;Nitasha;Nutan Jaswal;G. Singh

2010 International Conference on Recent Trends in Information, Telecommunication and Computing

Year: 2010 | Conference Paper |

Cited by: Papers (1)

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Circuit with double gates using independently controlled gates have been proposed to reduce the number of gates and to increase the logic densities per area. This paper introduces a vertical slit FET (double gate transistor) which has been demonstrated with the help of figures with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits...Show More

Full Subtractor Circuit Design with Independent Double Gate Transistor

Viranjay M. Srivastava;Shipra Kapoor;Nitasha;Nutan Jaswal;G. Singh

2010 International Conference on Recent Trends in Information, Telecommunication and Computing

Year: 2010 | Conference Paper |

Circuit Design with Independent Double Gate Transistors

Viranjay M. Srivastava;Nitant Saubagya;G. Singh

2010 International Conference on Advances in Computer Engineering

Year: 2010 | Conference Paper |

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Circuits with transistors using independently controlled gates have been designed to reduce the number of transistors and to increase the logic density per area. This paper proposed a full adder and substractor circuit with novel Vertical Slit Field Effect Transistor and unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. With the ...Show More

Circuit Design with Independent Double Gate Transistors

Viranjay M. Srivastava;Nitant Saubagya;G. Singh

2010 International Conference on Advances in Computer Engineering

Year: 2010 | Conference Paper |

Vth-control method in double gate field effect transistor domino circuits

Saeed Zeinolabedinzadeh;Behzad Ebrahimi;Ali Afzali-Kusha

2009 10th International Conference on Ultimate Integration of Silicon

Year: 2009 | Conference Paper |

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In this paper we investigate the possibility of power reduction in DGFET devices by means of Vth control technique applied for domino logics. Previously the effectiveness of Vth control method by means of back gate biasing has been investigated. In this paper we show that by special using back gate to control the threshold voltage we can save not only significant standby power but even considerabl...Show More

Vth-control method in double gate field effect transistor domino circuits

Saeed Zeinolabedinzadeh;Behzad Ebrahimi;Ali Afzali-Kusha

2009 10th International Conference on Ultimate Integration of Silicon

Year: 2009 | Conference Paper |

Nanoscale Vacuum Field Emission Triode With a Double Gate Structure

Xiao Wang;Chaofan Zheng;Tao Xue;Zhihua Shen;Minggang Long;Shengli Wu

IEEE Electron Device Letters

Year: 2022 | Volume: 43, Issue: 2 | Journal Article |

Cited by: Papers (9)

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A planar lateral Vacuum Field Emission Triode (VFET) with a double gate structure is proposed to improve the gate modulation characteristics in this letter. The preparation of this double gate structure is obtained by using the mature bottom gate VFET manufacturing process without any additional dedicated masks. The emission characteristics of the fabricated VFET under vacuum and atmosphere condit...Show More

Nanoscale Vacuum Field Emission Triode With a Double Gate Structure

Xiao Wang;Chaofan Zheng;Tao Xue;Zhihua Shen;Minggang Long;Shengli Wu

IEEE Electron Device Letters

Year: 2022 | Volume: 43, Issue: 2 | Journal Article |

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Jin-Woo Han;Chung-Jin Kim;Yang-Kyu Choi

IEEE Transactions on Electron Devices

Year: 2008 | Volume: 55, Issue: 6 | Journal Article |

Cited by: Papers (48)

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A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poisson's equation is obtained with the approximation that a vertical channel potential distribution is a cubic function of position. As a result, an analytical equation for the threshold voltage is derived from the proposed potential model. Different gate work function...Show More

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

Jin-Woo Han;Chung-Jin Kim;Yang-Kyu Choi

IEEE Transactions on Electron Devices

Year: 2008 | Volume: 55, Issue: 6 | Journal Article |

Steep Subthreshold Swing in Double Gate NCFET:A Simulation Study

Mooli Shashank Reddy;Tejendra Dixit;K P Pradhan

2021 IEEE Latin America Electron Devices Conference (LAEDC)

Year: 2021 | Conference Paper |

Cited by: Papers (1)

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The rapid increase in interest on Negative capacitance Field Effect Transistors(NCFETs) is due to its Low power applications. NCFETs stepsup the voltage between the oxide and ferroelectric capacitance due to reversing (i.e, amplification) effect of a ferroelectric (fe) layer[1]. These are designed in a way such that its Subthreshold swing overcomes the boltzmann limit. According to the Boltzmann t...Show More

Steep Subthreshold Swing in Double Gate NCFET:A Simulation Study

Mooli Shashank Reddy;Tejendra Dixit;K P Pradhan

2021 IEEE Latin America Electron Devices Conference (LAEDC)

Year: 2021 | Conference Paper |

Double Gate NCFET : A New Approach for Low Subthreshold Swing

Mooli Shashank Reddy;Tejendra Dixit;K P Pradhan

2020 5th IEEE International Conference on Emerging Electronics (ICEE)

Year: 2020 | Conference Paper |

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NCFETs(Negative Capacitance Field Effect Transistors) are commonly known for their Low Power Consumption[4]. As the name itself suggests that it uses a Negative Capacitance For the Voltage Amplification. This Amplification is due to the polarisation in the ferroelectric material, which is used as Negative Capacitance[5]. Due to the Orderly Alignment of the Dipoles in Ferroelectric material when an...Show More

Double Gate NCFET : A New Approach for Low Subthreshold Swing

Mooli Shashank Reddy;Tejendra Dixit;K P Pradhan

2020 5th IEEE International Conference on Emerging Electronics (ICEE)

Year: 2020 | Conference Paper |

Analytical study of double gate MOSFET: A design and performance perspective

Rupsa Roy;Joy Chowdhury;J. K. Das

2018 2nd International Conference on Inventive Systems and Control (ICISC)

Year: 2018 | Conference Paper |

Cited by: Papers (5)

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This paper presents an in depth study and analysis which shows that the Double gate MOSFET has emerged as one of the most favorable devices due to short channel effect immunity, off-current reduction ability and more scaling possibility. The devices with less than 0.1 μm gate length can maintain near ideal subthreshold factor. This paper also presents some new modifications in the existing devices...Show More

Analytical study of double gate MOSFET: A design and performance perspective

Rupsa Roy;Joy Chowdhury;J. K. Das

2018 2nd International Conference on Inventive Systems and Control (ICISC)

Year: 2018 | Conference Paper |

Analysis of Device Characteristics of Dual material Double gate Strained N-Channel MOSFET

Avinash Sharma;Sandeep Toshniwal;Rahul Pandey;Arun Dev Dhar Dwivedi

2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

Year: 2018 | Conference Paper |

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With the objective to achieve high drain current at lesser dimension in CMOS technology, device dimension reaches to Sub Nm region and undesirable effect such as short channel effect, high leakage current, DIBL are get introduced. And the desired characteristics become disturbed. As a solution to these problems, we have proposed a structure of Double material Double Gate strained n- MOSFET in this...Show More

Analysis of Device Characteristics of Dual material Double gate Strained N-Channel MOSFET

Avinash Sharma;Sandeep Toshniwal;Rahul Pandey;Arun Dev Dhar Dwivedi

2018 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

Year: 2018 | Conference Paper |

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Ankit Sharma;Akkala Arun Goud;Kaushik Roy

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 12 | Journal Article |

Cited by: Papers (47)

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In this letter, a sub-10-nm n-type GaSb-InAs heterojuction tunnel field-effect transistor (Het-j TFET), having n+-doped underlap layer of InAs between source and channel is proposed, which exhibits low subthreshold swing (SS) over a large range of currents. The proposed device is compared with conventional p-i-n GaSb-InAs Het-j TFET having the same physical gate length of 9 nm. Using ballistic tig...Show More

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Ankit Sharma;Akkala Arun Goud;Kaushik Roy

IEEE Electron Device Letters

Year: 2014 | Volume: 35, Issue: 12 | Journal Article |

Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications

Saurabh Mookerjea;Suman Datta

2008 Device Research Conference

Year: 2008 | Conference Paper |

Cited by: Papers (45) | Patents (1)

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This paper examines the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (VCC). Based on two-dimensional numerical drift-diffusion simulations, we show that 30 nm gate length (LG) InAs (indium arsenide) based TFETs can achieve Ion/Ioff of >4x10<...Show More

Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications

Saurabh Mookerjea;Suman Datta

2008 Device Research Conference

Year: 2008 | Conference Paper |

Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design

Kathy Boucart;Adrian M. Ionescu

ESSDERC 2007 - 37th European Solid State Device Research Conference

Year: 2007 | Conference Paper |

Cited by: Papers (36)

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This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the saturation of the barrier width na...Show More

Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design

Kathy Boucart;Adrian M. Ionescu

ESSDERC 2007 - 37th European Solid State Device Research Conference

Year: 2007 | Conference Paper |

Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe

Donghyun Kim;Tejas Krishnamohan;Lee Smith;H.-S. Philip Wong;Krishna C. Saraswat

2007 65th Annual Device Research Conference

Year: 2007 | Conference Paper |

Cited by: Papers (20) | Patents (3)

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Based on the complex bandstructure obtained by local empirical pseudopotential method (LEPM), we have developed a Band to Band Tunneling model (BTBT), which captures band structure information, all possible transitions between different valleys, energy quantization and quantized density of states. Theoretical model is verified by experimental study on tunnel diodes on various semiconductors. BTBT ...Show More

Band to Band Tunneling Study in High Mobility Materials : III-V, Si, Ge and strained SiGe

Donghyun Kim;Tejas Krishnamohan;Lee Smith;H.-S. Philip Wong;Krishna C. Saraswat

2007 65th Annual Device Research Conference

Year: 2007 | Conference Paper |

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

Marcus Weis;Andrzej Pfitzner;Dominik Kasprowicz;Rainer Emling;Thomas Fischer;Stephan Henzler;Wojciech Maly;Doris Schmitt-Landsiedel

2009 IEEE International Conference on IC Design and Technology

Year: 2009 | Conference Paper |

Cited by: Papers (18) | Patents (47)

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A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topology with a highly regular layout is presented and a significant memory cell area reduction can be achieved. Utilization of independent double gate transistors enhances the robustness for read and write op...Show More

Stacked 3-dimensional 6T SRAM cell with independent double gate transistors

Marcus Weis;Andrzej Pfitzner;Dominik Kasprowicz;Rainer Emling;Thomas Fischer;Stephan Henzler;Wojciech Maly;Doris Schmitt-Landsiedel

2009 IEEE International Conference on IC Design and Technology

Year: 2009 | Conference Paper |

Performance Analysis of Germanium Nanowire Tunneling Field Effect Transistors

N. Jain;E. Tutuc;S.K. Banerjee;L.F. Register

2008 Device Research Conference

Year: 2008 | Conference Paper |

Cited by: Papers (9)

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Tunneling field effect transistors (FET), consisting of gate tunable p-i-n (p-type-intrinsic-n-type) device structures, represent an attractive and realistic paradigm that can potentially provide relief to the increasing power dissipation in high performance electronic applications. Such devices possess a subthreshold slope (SS) smaller than the thermally limited 60 mV/decade, but also can suffer ...Show More

Performance Analysis of Germanium Nanowire Tunneling Field Effect Transistors

N. Jain;E. Tutuc;S.K. Banerjee;L.F. Register

2008 Device Research Conference

Year: 2008 | Conference Paper |

Band to Band Tunneling limited Off state Current in Ultra-thin Body Double Gate FETs with High Mobility Materials : III-V, Ge and strained Si/Ge

Donghyun Kim;Tejas Krishnamohan;Yoshio Nishi;Krishna C. Saraswat

2006 International Conference on Simulation of Semiconductor Processes and Devices

Year: 2006 | Conference Paper |

Cited by: Papers (9)

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We have developed new band to band tunneling (BTBT) model, which captures band structure information, all possible transitions between different valleys, energy quantization and quantized density of states (DOS). Minimum standby off-state currents (IOFF,MIN) are investigated in double gate (DG) MOSFETs with various high mobility materials, like GaAs, InAs, Ge and strained Si/Ge (s-Si/s-Ge) using t...Show More

Band to Band Tunneling limited Off state Current in Ultra-thin Body Double Gate FETs with High Mobility Materials : III-V, Ge and strained Si/Ge

Donghyun Kim;Tejas Krishnamohan;Yoshio Nishi;Krishna C. Saraswat

2006 International Conference on Simulation of Semiconductor Processes and Devices

Year: 2006 | Conference Paper |

Double gate movable body Micro-Electro-Mechanical FET as hysteretic switch: Application to data transmission systems

Daniel Grogg;Cedric Meinen;Dimitrios Tsamados;Huseyin C. Tekin;Maher Kayal;Adrian M. Ionescu

ESSDERC 2008 - 38th European Solid-State Device Research Conference

Year: 2008 | Conference Paper |

Cited by: Papers (6) | Patents (2)

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This paper reports on the fabrication, experimental characterization and data transmission application of a double-gate movable body FET. As its name suggests, the proposed movable-body Micro-Electro-Mechanical FET (MB-MEMFET) is a hybrid MEMS-semiconductor device that, in contrast with previously reported Suspended-Gate MOSFET, has a movable body separated by nano-size air gaps from two lateral f...Show More

Double gate movable body Micro-Electro-Mechanical FET as hysteretic switch: Application to data transmission systems

Daniel Grogg;Cedric Meinen;Dimitrios Tsamados;Huseyin C. Tekin;Maher Kayal;Adrian M. Ionescu

ESSDERC 2008 - 38th European Solid-State Device Research Conference

Year: 2008 | Conference Paper |

High-performance Si Nanowire FET with a semi gate-around structure suitable for integration

Soshi Sato;Hideyuki Kamimura;Hideaki Arai;Kuniyuki Kakushima;Parhat Ahmet;Kenji Ohmori;Keisaku Yamada;Hiroshi Iwai

2009 Proceedings of the European Solid State Device Research Conference

Year: 2009 | Conference Paper |

Cited by: Papers (5)

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Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO2 pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 muA at Vg- Vth=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate...Show More

High-performance Si Nanowire FET with a semi gate-around structure suitable for integration

Soshi Sato;Hideyuki Kamimura;Hideaki Arai;Kuniyuki Kakushima;Parhat Ahmet;Kenji Ohmori;Keisaku Yamada;Hiroshi Iwai

2009 Proceedings of the European Solid State Device Research Conference

Year: 2009 | Conference Paper |

A novel sub-20 nm depletion-mode double-gate (DMDG) FET

T. Krishnamohan;Z. Krivokapic;K.C. Saraswat

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

Year: 2003 | Conference Paper |

Cited by: Papers (3)

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We present a novel Depletion-Mode Double-Gate (DMDG) FET. As opposed to the conventional, un-doped body, double-gate MOSFETs, the DMDG device confines the carriers to the center of the device for all applied gate voltages. The device exhibits high mobility due to the carrier confinement in the very low E-field region in the center of the device. Simulations show very high I/sub on//I/sub off/ rati...Show More

A novel sub-20 nm depletion-mode double-gate (DMDG) FET

T. Krishnamohan;Z. Krivokapic;K.C. Saraswat

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

Year: 2003 | Conference Paper |

Planar double gate transistors with asymmetric independent gates

G. Ilicali;W. Weber;W. Rosner;L. Dreeskornfeld;J. Hartwich;J. Kretz;T. Lutz;J.-P. Mazellier;M. Stadele;M. Specht;J.R. Luyken;E. Landgraf;F. Hofmann;L. Risch;R. Kasmaier;W. Hansch

2005 IEEE International SOI Conference Proceedings

Year: 2005 | Conference Paper |

Cited by: Papers (3) | Patents (8)

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Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentall...Show More

Planar double gate transistors with asymmetric independent gates

G. Ilicali;W. Weber;W. Rosner;L. Dreeskornfeld;J. Hartwich;J. Kretz;T. Lutz;J.-P. Mazellier;M. Stadele;M. Specht;J.R. Luyken;E. Landgraf;F. Hofmann;L. Risch;R. Kasmaier;W. Hansch

2005 IEEE International SOI Conference Proceedings

Year: 2005 | Conference Paper |

A novel GaAs FET with double camel-like gate structure

IEEE Electron Device Letters

Year: 2005 | Volume: 26, Issue: 7 | Journal Article |

Cited by: Papers (3)

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Extremely high potential barrier height and gate turn-on voltage of a novel GaAs field-effect transistor with n/sup +//p/sup +//n/sup +//p/sup +//n double camel-like gate structure are demonstrated. The maximum electric field and potential barrier height of the double camel-like gate are substantially enhanced by the addition of another n/sup +//p/sup +/ layers in gate region, as compared with the...Show More

A novel GaAs FET with double camel-like gate structure

IEEE Electron Device Letters

Year: 2005 | Volume: 26, Issue: 7 | Journal Article |

Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?

2008 Device Research Conference

Year: 2008 | Conference Paper |

Cited by: Papers (2) | Patents (3)

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We have examined the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (VCC). Based on the two-dimensional numerical drift-diffusion simulations, we conclude that 30 nm gate length InAs (indium arsenide) based TFETs can achieve Ion/Ioff of > 4x104 with < 1 ps intrinsic delay at ...Show More

Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?

2008 Device Research Conference

Year: 2008 | Conference Paper |

The analysis of double doping polysilicon gate Lightly-doped-drain (LDD) MOSFET

Chang-yong Zheng

2010 The 2nd International Conference on Industrial Mechatronics and Automation

Year: 2010 | Conference Paper |

Cited by: Papers (2)

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A new type of field effect transistor (FET), the double doping polysilicon gate (DDPG) Lightly-doped-drain (LDD) MOSFET, is proposed and demonstrated. The gate of the DDPG LDD MOSFET adopts gate engineering. This novel gate structure takes advantage of material work function. The arrangement is such that the gate near the source is comprised of P-type polysilicon and the gate near the drain is N-t...Show More

The analysis of double doping polysilicon gate Lightly-doped-drain (LDD) MOSFET

Chang-yong Zheng

2010 The 2nd International Conference on Industrial Mechatronics and Automation

Year: 2010 | Volume: 2 | Conference Paper |

Power optimization of future transistors and a resulting global comparison standard

P. Kapur;R.S. Shenoy;A.K. Chao;Y. Nishi;K.C. Saraswat

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

Year: 2004 | Conference Paper |

Cited by: Papers (2)

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We report a global power minimization methodology for future transistors and use it as a comparison standard to quantify the relative and absolute impact of material and structural innovations on power and speed. In addition, we put the relative tradeoffs of device design in perspective of global metrics. In the process, we also develop and verify two key enabling models: (1) to calculate inverter...Show More

Power optimization of future transistors and a resulting global comparison standard

P. Kapur;R.S. Shenoy;A.K. Chao;Y. Nishi;K.C. Saraswat

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.

Year: 2004 | Conference Paper |

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