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Multi-level p+ tri-gate SONOS NAND string arrays
C. Friederich;M. Specht;T. Lutz;F. Hofmann;L. Dreeskornfeld;W. Weber;J. Kretz;T. Melde;W. Rosner;E. Landgraf;J. Hartwich;M. Stadele;L. Risch;D. Richter
2006 International Electron Devices Meeting
Year: 2006 | Conference Paper |
Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack...Show More
Lithography for the 32-nm Node and Beyond
2006 Bipolar/BiCMOS Circuits and Technology Meeting
Year: 2006 | Conference Paper |
This review article presents, discusses and compares three emerging photo lithography techniques for use in future BiCMOS fabrication processes: EUV lithography, e-beam direct write, and nano imprint. Specific challenges are discussed and the state-of-the-art is illustrated with respect to bipolar device scalingShow More
Planar double gate transistors with asymmetric independent gates
G. Ilicali;W. Weber;W. Rosner;L. Dreeskornfeld;J. Hartwich;J. Kretz;T. Lutz;J.-P. Mazellier;M. Stadele;M. Specht;J.R. Luyken;E. Landgraf;F. Hofmann;L. Risch;R. Kasmaier;W. Hansch
2005 IEEE International SOI Conference Proceedings
Year: 2005 | Conference Paper |
Planar double-gate field effect transistors with asymmetric (p++/n++) independent gates down to 55nm physical gate lengths are successfully fabricated. A fabrication concept, epi-before-bonding, is introduced and demonstrated to be highly successful in achieving ultra-thin and planar Si bodies. Various modes of operations are extensively analyzed and compared to 2D simulations. It is experimentall...Show More
20 nm tri-gate SONOS memory cells with multi-level operation
M. Specht;U. Dorda;L. Dreeskornfeld;J. Kretz;F. Hofinann;M. Stadele;R.J. Luyken;W. Rosner;H. Reisinger;E. Landgraf;T. Schulz;J. Hartwich;R. Kommling;L. Risch
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
Year: 2004 | Conference Paper |
Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/s...Show More
Use of LPCVD TEOS as a direct bonding material for layer transfer: densified vs. undensified
G. Ilicali;W. Rosner;W. Weber;S. Boz;L. Dreeskornfeld;J. Hartwich;J. Kretz;J.R. Luyken;E. Landgraf;F. Hofmann;L. Risch;W. Hansch
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)
Year: 2004 | Conference Paper |
Cited by: Papers (2)
In this work, LPCVD deposited TEOS, both densified (DT)/undensified (UDT) and structured/non-structured cases are systematically studied and optimized. We have investigated different oxide type bonding materials for layer transfer applications under various processing conditions. It has been shown that very high bond strengths are achievable with UDT for a short-time and low-temperature annealing....Show More
Novel dual bit tri-gate charge trapping memory devices
M. Specht;R. Kommling;F. Hofmann;V. Klandzievski;L. Dreeskornfeld;W. Weber;J. Kretz;E. Landgraf;T. Schulz;J. Hartwich;W. Rosner;M. Stadele;R.J. Luyken;H. Reisinger;A. Graham;E. Hartmann;L. Risch
Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devic...Show More
Off current adjustment in ultra-thin SOI MOSFETs
J. Hartwich;L. Dreeskornfeld;F. Hofmann;J. Kretz;E. Landgraf;R.J. Luyken;M. Specht;M. Stadele;T. Schulz;W. Rosner;L. Risch
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)
Year: 2004 | Conference Paper |
Cited by: Papers (2)
This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25 nm and silicon thicknesses of 25 nm and 16 nm have been analysed. Gate oxide thicknesses of 2.5 nm and 1.8 nm have also been compared. We demonstrate off current adjustment by chann...Show More
A comprehensive study of corner effects in tri-gate transistors
M. Stadele;R.J. Luyken;M. Roosz;M. Specht;W. Rosner;L. Dreeskornfeld;J. Hartwich;F. Hofmann;J. Kretz;E. Landgraf;L. Risch
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)
Year: 2004 | Conference Paper |
We have performed extensive 2D and 3D device simulations to assess the impact of gate and drain voltages, channel doping, discrete impurity effects, and the device dimensions on the electron density accumulation in the corner regions of tri-gate transistors. For channel doping concentrations higher than 10/sup 18/ cm/sup -3/, these 'corner effects' are found to dominate the device behavior. They a...Show More
Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications
M. Specht;R. Kommling;L. Dreeskornfeld;W. Weber;F. Hofmann;D. Alvarez;J. Kretz;R.J. Luyken;W. Rosner;H. Reisinger;E. Landgraf;T. Schulz;J. Hartwich;M. Stadele;V. Klandievski;E. Hartmann;L. Risch
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.
Year: 2004 | Conference Paper |
Fully-depleted tri-gate oxide-nitride-oxide (ONO) transistor memory cells with very short gate lengths in the range L/sub G/ = 30 - 80 nm have been fabricated for the first time. The devices show very good electrical characteristics and have been optimized successfully for high density applications. A NAND-type array organization is proposed and solutions to integration issues are given. In additi...Show More
Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications
M. Specht;R. Kommling;L. Dreeskornfeld;W. Weber;F. Hofmann;D. Alvarez;J. Kretz;R.J. Luyken;W. Rosner;H. Reisinger;E. Landgraf;T. Schulz;J. Hartwich;M. Stadele;V. Klandievski;E. Hartmann;L. Risch
Year: 2004 | Conference Paper |
Nanoscale FinFETs for low power applications
W. Rosner;E. Landgraf;J. Kretz;L. Dreeskornfeld;H. Schafer;M. Stadele;T. Schulz;F. Hofmann;R.J. Luyken;M. Specht;J. Hartwich;W. Pamler;L. Risch
International Semiconductor Device Research Symposium, 2003
Year: 2003 | Conference Paper |
FinFETs were the most favourable double gate transistor for the future CMOS device demands due to their improved turn off behaviour caused by better electrostatic channel control, suits especially for battery powered hand held applications. The device was fabricated with an Eltran SOI wafers. Its transfer characteristics reveals its suitability for its application in low power applications.Show More
Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics
M. Specht;H. Reisinger;M. Stadele;F. Hofmann;A. Gschwandtner;E. Landgraf;R.J. Luyken;T. Schulz;J. Hartwich;L. Dreeskornfeld;W. Rosner;J. Kretz;L. Risch
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.
Year: 2003 | Conference Paper |
Replacing oxide-nitride-oxide (ONO) dielectrics in charge trapping memories such as SONOS (silicon/ONO/silicon) and NROM (nitrided read only memory) by high-k materials potentially offers improved scaling properties of the devices. In particular, a high dielectric constant of at least one of the three layers allows one to reduce the total equivalent oxide thickness (EOT) thus achieving the same pr...Show More
Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]
R.J. Luyken;M. Specht;W. Rosner;J. Hartwich;F. Hofmann;L. Dreeskornfeld;E. Landgraf;T. Schulz;M. Stadele;J. Kretz;L. Risch
ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.
Year: 2003 | Conference Paper |
Cited by: Papers (1)
The leakage mechanisms in fully depleted (FD) SOI transistors with undoped channel are investigated. These devices - contrary to partially depleted devices - show a strong V/sub DS/ dependence of the leakage currents. Energy balance simulations, including band to band tunneling effects and impact ionization, have been carried out. Contrary to drift diffusion calculations, these simulations can acc...Show More
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