Test Whats new message.
Scheduled Maintenance on Monday 1/13/2025
Single article sales and account management will be unavailable from 5:00 AM - 7:00 PM ET (09:00 - 23:00 UTC). We apologize for the inconvenience.
IEEE International Workshop on Electronic Design, Test and Applications (DELTA)
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
13-15 Jan. 2010
Showing 1-25 of 68
Proceedings
The proceedings of this conference will be available for purchase through Curran Associates.
Electronic Design, Test, and Application (DELTA), 2010 Fifth IEEE International Symposium on
- Print on DemandPurchase at Partner
Sort By
[Front cover]
[Title page i]
[Title page iii]
[Copyright notice]
Table of contents
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs
Publication Year: 2010,Page(s):3 - 7
Cited by: Papers (6)
Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed ...Show More
(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems
Manuel J. Barragán;Gloria Huertas;Adoración Rueda;José L. Huertas
Publication Year: 2010,Page(s):8 - 13
Cited by: Papers (5)
This paper presents an overview of test techniques that offer promising features when Built-In-Self-Test (BIST) must be applied to complex intgrated systems including analog, mixed-signal and RF parts. Emphasis is on techniques exhibiting a good trade-off between test requirements (basically in terms of signal accuracy and frequency) and test quality.Show More
Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits
Publication Year: 2010,Page(s):14 - 19
Cited by: Papers (7)
In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical defects b...Show More
Enabling False Path Identification from RTL for Reducing Design and Test Futileness
Publication Year: 2010,Page(s):20 - 25
Cited by: Papers (3)
Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restric...Show More
Least-squares Optimal Interpolation for Fast Image Super-resolution
Publication Year: 2010,Page(s):29 - 34
Cited by: Papers (6)
Image super-resolution is generally regarded as consisting of three steps - image registration, fusion, and deblurring. This paper presents a novel technique for resampling a non-uniformly sampled image onto a uniform grid that can be used for fusion of translated input images. The proposed method can be very fast, as it can be implemented as a finite impulse response filter of low order (10th ord...Show More
Design, Fabrication and Characterization of Asymmetric Fabry-Perot Modulator for Large Size Optical Shutter
Byung Hoon Na;Kwang Mo Park;Sooraj R.;Bong Kyu Jeong;Young Min Song;Yong Tak Lee;Chang Soo Park
Publication Year: 2010,Page(s):35 - 38
Cited by: Patents (1)
We report the growth, fabrication and characterization of asymmetric Fabry-Perot modulators which function as optical shutter which can be used in 3-D imaging. By choosing appropriate electrode geometry, a reduction in parasitic capacitance was achieved. The results reveal that such devices are promising candidates as optical shutter for 3-D imaging applications.Show More
In this paper, a hybrid CMOS pulse width modulation (PWM) digital pixel sensor (DPS) is proposed. In order to reduce the pixel area, the proposed architecture requires only a two bit on-pixel memory while placing the remaining six bits outside the array, assuming a common resolution of eight bits. This new architecture reduces the size of the pixel significantly as the memory requirement at pixel ...Show More
A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording
Publication Year: 2010,Page(s):51 - 53
Cited by: Papers (8)
This paper presents a low voltage, low noise and very low frequency amplifier suitable for bio-signal recording. The amplifier requires only ±0.6 V supply and consumes 1.24 ¿W, with a 75.5 dB gain over a bandwidth covering a range of frequencies from some hundreds of mHz to 19 kHz. A UMC 0.13 ¿m CMOS process is used in design and simulation. The new solution is suitable for a variety of biomedical...Show More
A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques
Publication Year: 2010,Page(s):54 - 57
In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital techniqu...Show More
Energy-aware Filter Cache Architecture for Multicore Processors
Publication Year: 2010,Page(s):58 - 62
Cited by: Papers (3)
Energy consumption as well as performance should be considered when designing high-performance multicore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential for high-performance multicore processors. In this paper, we propose new instruction cache...Show More
Independent Component Analysis Applied to Watermark Extraction and its Implemented Model on FPGAs
Publication Year: 2010,Page(s):71 - 76
Cited by: Papers (1)
Most of published audio watermark algorithms are suffered a trade-off between inaudibility and detectibility, and the detection performance depends greatly on the strength of noise added by communication channels. This work introduces an audio watermarking method that can overcome this challenge, i.e. allows increasing watermark strength while preserving inaudibility. The scheme uses psychoacousti...Show More
Algorithm Transformation for FPGA Implementation
Publication Year: 2010,Page(s):77 - 81
Cited by: Papers (7)
High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by porting them to an FPGA based hardware implementation. Porting does not always result in efficient architectures as the original algorithms are usually developed and optimized to run on a serial processor. To obtain an effi...Show More
Designing a Harware Accelerator for Face Recognition Using Vector Quantization and Principal Component Analysis as a Component of SoPC
Publication Year: 2010,Page(s):82 - 86
A flexible hardware accelerator for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real- time image compression and recognition applications. In the system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. T...Show More
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis
Toshinobu Matsuba;Yuko Hara;Hiroyuki Tomiyama;Shinya Honda;Hiroaki Takada
Publication Year: 2010,Page(s):87 - 92
Cited by: Papers (1)
A novel high-level synthesis (HLS) technique to improve the clock frequency is presented. Our technique aims at the reduction of the clock period by eliminating interconnections, specifically multiplexers (MUXs). MUXs are generally inserted before shared functional units and shared registers. However, MUXs are also inserted before a register even if the register is not shared by multiple variables...Show More
16-QAM Transmitter and Receiver Design Based on FPGA
Publication Year: 2010,Page(s):95 - 98
Cited by: Papers (10)
The FPGA technology has been playing a considerable role in portable and mobile communication. This is due to the features of flexibility, accuracy and configurability in designing and implementation. The paper presents a complete design for a 16-QAM transmitter and receiver based on the Virtex4 FPGA Kit. The implemented system can be applied in particle. Based on the principles of carrier synchro...Show More
A More Precise Model of Noise Based PCMOS Errors
Arun Bhanu;Mark S.K. Lau;Keck-Voon Ling;Vincent J. Mooney III;Anshul Singh
Publication Year: 2010,Page(s):99 - 102
Cited by: Papers (14)
In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterizatio...Show More
A Smart CMOS Image Sensor with On-chip Hot Pixel Correcting Readout Circuit for Biomedical Applications
Publication Year: 2010,Page(s):103 - 107
One of the most recent and exciting applications for CMOS image sensors is in the biomedical field. In such applications, these sensors often operate in harsh environments (high intensity, high pressure, long time exposure), which increase the probability for the occurrence of hot pixel defects over their lifetime. This paper presents a novel smart CMOS image sensor integrating hot pixel correctin...Show More
Proceedings
The proceedings of this conference will be available for purchase through Curran Associates.
Electronic Design, Test, and Application (DELTA), 2010 Fifth IEEE International Symposium on
- Print on DemandPurchase at Partner
IEEE Account
Purchase Details
Profile Information
Need Help?
- US & Canada: +1 800 678 4333
- Worldwide: +1 732 981 0060
- Contact & Support
- About IEEE Xplore
- Contact Us
- Help
- Accessibility
- Terms of Use
- Nondiscrimination Policy
- Sitemap
- Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity.
© Copyright 2025 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.