Rule Check of pad Placement in IC Layout With Yolo V3

Deep learning has been widely applied in the image processing. However, few works have been done on the layout check of integrated circuits. This paper tests the capability of Yolo v3 in identifying the rule violation of the IC layout. The test case is the VDD and VSS pad arrangement of a 44-pin die. The result is quite positive. All error spots in the test set have been identified. Even the layout is irregularly shaped, Yolo can still find all errors. This work shows that deep learning has great potential in integrated circuit layout inspection, which is worthy of further exploration.

Introduction

Layout check is critical for the success of type-out of integrated circuits. Calibre of mentor graphic is popular commercial tool to perform layout check. It explores the original design data of the IC layout and identifies spots of rule violation. Another possible way for the layout check is through the visual technology. Errors can be found by looking at the images of the chip layout. Visual inspection is friendly for human nature. It helps the proj ect manager to understand more precisely the work of the design engineers and even to point out the mistakes in the work.