A 6.22pJ/conv-step Split Design and Subtractor Based Binary Search ADC

This paper presents the design of 8-bit asynchronous based binary search analog to digital converter (ADC) using split design topology. In the proposed work, the 8 bits had been realized using two stages of 4 bits each with a subtractor in between. The use of such asynchronous design had resulted in reduction of switching network, reduced number of comparator and improvement in speed and chip area. The proposed 8-bit ADC is designed in 0.18 μm CMOS process and realizes conversion rate of approximately 230 MS/s while consuming 11.5 mW of power with 50% saving of chip area and 16% improvement of speed in comparison to other design. The proposed design achieves 6.22 pJ/conv-step of Walden FOM.

I. Introduction

The digital transmission is the most preferred form in today's communication system because of its better signal integrity in the presence of noise [1]. The efficiency of transmission demands high speed, low chip area and low power [2] analog to digital converter (ADC) in order to maintain lifetime of battery powered devices [3]. In flash ADC, the comparator requirement are exponentially related to resolution which results in more hardware area and high power dissipation [4]. Hence, in the interest of minimizing chip area and power consumption, flash ADC is not preferred for higher resolution and eventually gave path to successive approximation register (SAR) ADC [5] wherein one comparator is used resulting in reduced chip area and less power dissipation at the cost of reduced speed [6]–[7]. Later the requirement of both high speed and low power was achieved by yet another entrant defined by the name binary search (BS) ADC that adopt the advantage of both flash and SAR ADC architectures.