Contents I. Introduction
Junctionless transistors (JLT) do not have any pn junction in the source-channel-drain path and have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region i.e., junctionless transistors avoid the ultrahigh doping concentration gradients at the junctions and high thermal budgets, and hence their fabrication steps are comparatively easier than junction-based metal oxide field-oxide transistors (JB MOSFETs). They offer low OFF-state currents and hence can be scaled to lower channel lengths compared to JB MOSFETs. JLT has near ideal subthreshold slope (SS~60 mV/dec), high ON-state to OFF-state current ratio , low drain induced barrier lowering (DIBL) etc. [1]. The transconductance in JLT is, however, inferior compared to similar dimension JB transistors. Device variability and the parasitic source/drain resistances are acknowledged as some important limitations of the JL nanowire field-effect transistors. Although fabrication steps for a JLT is reported to be moderately simpler compared to conventional inversion mode devices; highly doped uniform channel is difficult to realize cost effectively.
