I. Introduction
Capacitance–voltage (–) simulation and extraction tools have been previously developed for Si-based MOS gate-stack analysis including those with various models to account for quantization effects. The most widely used among these is the North Carolina State University (NCSU) CVC Program [1]. This program has been heavily used, since its publication to aid with gate-stack process development by enabling the extraction of equivalent oxide thickness (EOT), doping density, and the flat band voltage. However, CVC was implemented assuming silicon’s band structure only and is therefore inaccurate when used for MOS devices based on any other semiconductor. Additionally, because Si has such a high-quality native oxide with very low interface defect density, CVC was developed without the capability of extracting a detailed distribution as a function of energy.