A novel partially insulated junctionless transistor for low power nanoscale digital integrated circuits

In this paper, a novel device structure named as partially insulated (Pi-OX) junctionless transistor (JLT) is proposed and the simulated results below 20 nm have been compared with existing silicon-on-insulator (SOI) JLT. Further, drain-induced barrier lowering (DIBL), subthreshold swing (SS), on-state drive current (I_ON), off-state leakage current (I_OFF), I_ON/I_OFF ratio and static power dissipation (P_STAT) of the proposed Pi-OXJLT and SOIJLT has also been compared. It has been found that, I_OFF, DIBL and SS in the case of proposed Pi-OXJLT are reduced by 57%, 17% and 10% respectively over the existing SOIJLT device. The fabrication flow of the proposed Pi-OXJLT is proposed.