Contents I. Introduction
Lately, researchers, innovators and chip makers have been working towards the shrinking the size of the MOSFETs to sub-20 nm regimes. The conventional MOSFET suffers from the challenges such as short channel effects (SCE) and most importantly in the fabrication of the device. Due to the presence of junction in the conventional MOSFET, fabrication of junction with high degree of doping gradation is complex, increasing fabrication cost [1]–[4]. Alternatively, junctionless transistors (JLT) have been proposed in the literature, which do not contain junctionx at the source/drain-to-channel interface. The important advantages of the junctionless scheme are reduced fabrication cost (by avoiding high gradation junction) and reduced short channel effects (SCEs) [5]–[7].
