Comprehensive understanding of random telegraph noise with

Physical modeling of transient and frequency domain noise simulation for random telegraph noise (RTN) is conducted, considering discretized traps and energy transition in insulator. The models are implemented in a 3D device simulator to consider the device structure effect and bias effect universally. Trap density and trap distribution in insulator are predicted quantitatively with comparison of measured data and simulated data. In addition, we present negative pre-pulse effect for RTN reduction.

Introduction

RTN is becoming a critical issue for reliability of analog CMOS, digital CMOS, and NAND-Flash memory [1], [2], since the amount of current change due to single charge trap/de-trap becomes larger with shrinking of the device size. Therefore, reduction of RTN becomes essential technology for the continued scaling of the devices.