A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation

Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by $15\times $ to over $23.8\times $ depending on performance level. Alternatively, LT improves performance by $2.4\times $ (high-power, high-performance) $- 7.0\times $ (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in $V_{\text {th}}$ variation to leverage benefits at cryogenic temperatures.

I. Introduction

Driven by the burgeoning needs of artificial intelligence and deep learning, the computing demand is escalating at an unprecedented pace. However, the performance boost from technology scaling is stagnant. Increased leakage currents restrict reductions in threshold voltage (), while heightened dynamic power constrains the elevation of the supply voltage (). Consequently, these factors collectively limit performance improvements. Furthermore, the threshold voltage () cannot be scaled down aggressively, complicating efforts to reduce the power-supply voltage () for power conservation. Moreover, enhancing performance by increasing the clock frequency is becoming increasingly challenging as the dynamic power consumption rises accordingly [2]. Thus, innovative approaches are needed to advance modern transistors and interconnect to fulfill the exponentially growing computing demand.