Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau–Lifshitz–Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%–87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.

I. Introduction

Rapid growth in memory intensive workloads, such as machine learning, data analytics, and database applications, is driving the need for increased memory capacity, bandwidth, and performance. Several new memory technologies have emerged, and each displaying great advantages over traditional memory solutions. Among these candidates, magnetic random access memories (MRAMs) have been recognized as the most viable for high performance computing due to their high speed, low energy, and practically unlimited endurance [1]. Such advantages have driven the development of several flavors of MRAM based upon different write mechanisms; e.g., those based upon magnetic-field switching (Toggle-MRAM) [2], those based on the spin-transfer torque effect (STT-MRAM) [3], [4], [5], the voltage-controlled magnetic anisotropy effect (VCMA-MRAM) [6], [7], [8], [9], and the spin-orbit-torque (SOT-MRAM) effect [10], [11], [12]. Advancing upon these designs, the combination of multiple mechanisms for memory has also been proposed. In particular, the VCMA combined with the SOT effect is anticipated as the next-generation MRAM, resolving many of the challenges of VCMA and SOT MRAMs, as well as demonstrating 40% improvement in density and improvement in energy efficiency compared to the in- production STT-MRAM. Combined switching of voltage-controlled (VC) and SOT has been observed in [13], [14], [15], [16], and [17], and analysis of its operating margin has been carried out [13], [18], [19], [20]. The cooperation of the two mechanisms not only leads to improved memory performance with high selectivity, low energy, and compact area [21] but also broadens its range of applications. Those ranging from logics [22], [23], [24], [25], computing in memory [17], [26], [27], neural networks [28], [29], [30], as well as unconventional computing schemes [31], [32], [33] have been proposed.