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Showing 1-25 of 9,617 resultsfor "Index Terms":Specific Hardware
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Securing AI Hardware: Challenges in Detecting and Mitigating Hardware Trojans in ML Accelerators
Kevin Immanuel Gubbi;Inderpreet Kaur;Abdallah Hashem;Sai Manoj P D;Houman Homayoun;Avesta Sasan;Soheil Salehi
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2023 | Conference Paper |
Cited by: Papers (6)
Artificial Intelligence (AI) has transformed multiple industries, creating specialized hardware for AI/Machine Learning (ML) workloads. These hardware accelerators have become prevalent in healthcare, scientific computing, space ex-ploration, the military, and consumer electronics. However, using AI hardware in critical systems can pose a significant risk due to potential attack vectors that malic...Show More
AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors
2007 IEEE Workshop on Signal Processing Systems
Year: 2007 | Conference Paper |
We present an ASIP (application-specific instruction-set processor) approach for H.264 implementation having novel coprocessors. We have previously proposed the video specific instruction-set processor (VSIP) for H.264/AVC. To improve performance of motion estimation (ME) further, we propose a new improved ME accelerator using the modified normalized partial distortion search (MNPDS) algorithm. Th...Show More
Synthesis of application specific instructions for embedded DSP software
Hoon Choi;Jong-Sun Kim;Chi-Won Yoon;In-Cheol Park;Sung Ho Hwang;Chong-Min Kyung
IEEE Transactions on Computers
Cited by: Papers (44)
Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, whil...Show More
High-Level Synthesis from C vs. a DSL-Based Approach
Cristiano Bacelar de Oliveira;Joao M. P. Cardoso;Eduardo Marques
2014 IEEE International Parallel & Distributed Processing Symposium Workshops
Year: 2014 | Conference Paper |
Cited by: Papers (6)
Field-Programmable Gate Arrays (FPGAs) are able to provide hardware accelerators still maintaining the required programmability. However, the advantages of using FPGAs still depend on the expertise of developers and their knowledge of Hardware Description Languages (HDLs). Although High-level Synthesis (HLS) tools have been developed in order to minimize this problem, they commonly present solutio...Show More
Guest Editors' Introduction: What Kinds of Nails Need a Domain-Specific Hammer?
Jonathan Sprinkle;Marjan Mernik;Juha-Pekka Tolvanen;Diomidis Spinellis
Domain-specific techniques, languages, tools, and models, such as Fortran and Cobol can easily be viewed as domain-specific languages for scientific and business computing, respectively. Their domain is just very wide. What has changed is the technology for creating domain-specific languages (DSLs). Now it is easier to define languages and get tool support for narrower domains. Such focus offers i...Show More
An approach to concurrent development of device drivers and device controller
Edson B. Lisboa;Luciano Silva;Thiago Lima;Igino Chaves;Edna Barros
2009 11th International Conference on Advanced Communication Technology
Year: 2009 | Conference Paper |
Cited by: Papers (2)
Embedded Systems must communicate with different peripheral devices to provide easy interactivity and mobility. The communication structure combines hardware and software solutions. The design of a communication structure demands great effort, long time, tends to cause many errors and has relevant impact in system performance. To minimize these questions, this paper presents an approach to concurr...Show More
LLM4SecHW: Leveraging Domain-Specific Large Language Model for Hardware Debugging
Weimin Fu;Kaichen Yang;Raj Gautam Dutta;Xiaolong Guo;Gang Qu
2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
Year: 2023 | Conference Paper |
Cited by: Papers (12)
This paper presents LLM4SECHW, a novel framework for hardware debugging that leverages domain-specific Large Language Model (LLM). Despite the success of LLMs in automating various software development tasks, their application in the hardware security domain has been limited due to the constraints of commercial LLMs and the scarcity of domain-specific data. To address these challenges, we propose ...Show More
Towards "general purpose" brain-inspired computing system
Tsinghua Science and Technology
Cited by: Papers (11)
Brain-inspired computing refers to computational models, methods, and systems, that are mainly inspired by the processing mode or structure of brain. A recent study proposed the concept of "neuromorphic completeness" and the corresponding system hierarchy, which is helpful to determine the capability boundary of brain-inspired computing system and to judge whether hardware and software of brain-in...Show More
A Co-design Flow for Reconfigurable Embedded Computing System with RTOS Support
2009 International Conference on Embedded Software and Systems
Year: 2009 | Conference Paper |
Cited by: Papers (2)
Reconfigurable system provides both flexibility of software and performance of hardware. It is a significant trend in embedded application domain. Some new reconfigurable technologies and technology-dependent tools have been developed, but the whole design flow for run-time reconfigurable systems with real-time operating system support is not proposed. RTOS plays an important role in the system an...Show More
The Feedback of the Completion Time Distribution to the Teaching Effect Based on the Remote Hardware Experiment System
2018 13th International Conference on Computer Science & Education (ICCSE)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
We have developed a new experimental device to support online experimentation of hardware experiments. After many years of computer education practice and the rapid development of computers, there are many problems with traditional online experiment methods, especially in hardware-related teaching. In addition, we have developed a corresponding software system to help students access laboratory eq...Show More
An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training
Deep Neural Networks (DNNs) have been widely used in various artificial intelligence (AI) applications due to their overwhelming performance. Furthermore, recently, several algorithms have been reported that require on-device training to deliver higher performance in real-world environments and protect users’ personal data. However, edge/mobile devices contain only limited computation capability w...Show More
Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification
The wide usage of hardware intellectual property cores from untrusted vendors has raised security concerns for system designers. Existing solutions for functionality testing and verification do not usually consider the presence of malicious logic in hardware. Formal methods provide powerful solutions for detecting malicious behaviors in hardware. However, they suffer from scalability issues and ca...Show More
Behavioral synthesis of digital filters using attribute grammars
George Economakos;George Papakonstantinou;Panayiotis Tsanakas
9th European Signal Processing Conference (EUSIPCO 1998)
Year: 1998 | Conference Paper |
Recently, a formal framework to perform behavioral synthesis using attribute grammars has been presented, its main advantages being modularity and declarative notation in the development of design automation environments. From a practical point of view, most modern behavioral synthesizers are best suited for the development of special purpose hardware to implement digital signal processing algorit...Show More
Cache miss reduction through hardware-assisted loop optimization
Kang Zhao;Jinian Bian;Chenqian Jiang;Sheqin Dong;Satoshi Goto
2008 12th International Conference on Computer Supported Cooperative Work in Design
Year: 2008 | Conference Paper |
To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instru...Show More
RISC-V processors design: a methodology for cores development
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
One approach to the use of the practices of CMMIDEV V1.3 level 2 in a process of development of embedded systems
IISA 2014, The 5th International Conference on Information, Intelligence, Systems and Applications
Year: 2014 | Conference Paper |
Currently the major concern of software engineering is the quality of Embedded Computing Systems, as they are a classification of software that are strongly present in our daily lives so that often we do not realize. Are composed of hardware and software encapsulated and generally dedicated to a single activity a major characteristic of such systems is the ability to perform very important tasks w...Show More
Temporal Staging for Correct-by-Construction Cryptographic Hardware
2024 International Workshop on Rapid System Prototyping (RSP)
Year: 2024 | Conference Paper |
There is a conceptual divide between the ways cryptographic algorithms are defined (i.e., informal imperative pseudocode) and commodity hardware design languages (e.g., Verilog). How does one even begin to compare a pseudocode to an HDL design that purports to implement it in hardware? Bridging this divide requires substantial manual intervention and, consequently, “shrinking the divide” can drast...Show More
ASIP approach for implementation of H.264/AVC
Asia and South Pacific Conference on Design Automation, 2006.
Year: 2006 | Conference Paper |
Cited by: Papers (8)
This paper presents an application-specific instruction set processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra prediction, deblocking filter, integer transform, etc. In addition, the proposed ASIP has hardware accelerators for inter prediction and entropy coding. Performance comparisons show a significant improvement compared with existi...Show More
Survey on evolvable hardware and embryonic hardware
2013 IEEE 11th International Conference on Electronic Measurement & Instruments
Year: 2013 | Conference Paper |
Cited by: Papers (5)
Bio-inspired hardware is a circuit with self-organizing, self-healing and adaptive ability referring the concepts in biology. This paper provides a new method to improve the reliability of electronic equipment. Evolvable hardware and embryonic hardware are the two research branches of bio-inspired hardware. The basic connotations of evolvable hardware and embryonic hardware are introduced, and the...Show More
Transitioning to Chisel in University Education: Experiences and Lessons Learned
2023 IEEE Nordic Circuits and Systems Conference (NorCAS)
Year: 2023 | Conference Paper |
Cited by: Papers (1)
Hardware description languages are essential for specifying, designing, and verifying digital systems. VHDL and Verilog have been the predominant hardware description languages, but they present educational challenges due to their steep learning curve and low-level nature. Conversely, Chisel, a language embedded in Scala, offers a high-level, software-like approach to hardware design. This paper p...Show More
HRHS: A High-Performance Real-Time Hardware Scheduler
Danesh Derafshi;Amin Norollah;Mohsen Khosroanjam;Hakem Beitollahi
This article represents an on-line time-predictable distributed hardware scheduler solution, suitable for many-core systems. We have partitioned the Main scheduler into uniform Partial schedulers to achieve a significant gain in term of performance and scalability, while software scheduling solutions impose excessive delays (in order of thousands of clock cycles) to a system. Although we have cons...Show More
With the rapid development of deep learning techniques, the security issue for Neural Network (NN) systems has emerged as an urgent and severe problem. Hardware Trojan attack is one of the threatens, which provides attackers backdoors to control the prediction results of NN systems. This paper proposes a sequence triggered hardware Trojan. Normal images but with specific sequence are used to trigg...Show More
Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging
Holger Scherl;Stefan Hoppe;Markus Kowarschik;Joachim Hornegger
2008 ACM/IEEE 30th International Conference on Software Engineering
Year: 2008 | Conference Paper |
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficient clinical workflow it is inevitable to meet high performance requirements. Hence, the usage of hardware acceleration is mandatory. The software architecture of the reconstruction system is required to be modular in a sen...Show More
Exploration of the Computer Hardware Experiment teaching method based on the cloud platform
2016 IEEE Frontiers in Education Conference (FIE)
Year: 2016 | Conference Paper |
Cited by: Papers (3)
This paper presents a new method for Computer Hardware Experiment teaching. Previous hardware experiments of computer is built on a computer connected to a hardware equipment locally, and then student operate the hardware devices on the switches, buttons, etc. to carry out experiments and verify the developed hardware code is correct. Such experimental methods have lots of significant limitations....Show More
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