Transitioning to Chisel in University Education: Experiences and Lessons Learned

Hardware description languages are essential for specifying, designing, and verifying digital systems. VHDL and Verilog have been the predominant hardware description languages, but they present educational challenges due to their steep learning curve and low-level nature. Conversely, Chisel, a language embedded in Scala, offers a high-level, software-like approach to hardware design. This paper presents our experience at the Technical University of Denmark (DTU) transitioning from VHDL to Chisel for selected courses and projects. We discuss the challenges faced in using VHDL and Verilog as entry-level languages, and we highlight the benefits and lessons learned from the transition to Chisel, including improved accessibility and efficiency in learning hardware design. This paper contributes to the ongoing discussion on languages for hardware description in education and provides insights into the advantages of adopting Chisel as an alternative language. The transition resulted in overwhelmingly positive outcomes, with improved student understanding, productivity, satisfaction, and performance.

I. Introduction

Hardware description languages (HDL) play a crucial role in the specification, design, and verification of modern digital systems. HDLs describe hardware behavior and structure, allowing designers to model and simulate digital circuits before their physical implementation. This enables efficient and systematic design methodologies, reducing time-to-market and ensuring reliable and optimized hardware designs. Historically, HDLs have evolved from simple register-transfer level languages to powerful and expressive ones describing intricate digital systems. Two prominent HDLs are currently widely adopted in the industry are VHDL (VHSIC HDL) and Verilog.