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Showing 1-25 of 4,632 resultsfor "Index Terms":Counter Value
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A TVaR-EGARCH-POT Based Market Financing Risk Evaluation of the New OTC (Over the Counter) Market
2018 2nd International Conference on Data Science and Business Analytics (ICDSBA)
Year: 2018 | Conference Paper |
Cited by: Papers (1)
In the process of Chinese industry conversion and upgrading, technological innovation enterprises play important roles. Technology enterprises could not develop without the support of financial market, and risk involved in their financing processes directly affects investment inclinations of capital market. Through establishing a TVaR-EGARCH-POT model, this investigation measured market financing ...Show More
Real-Time Detection on Cache Side Channel Attacks using Performance Counter Monitor
2019 International Conference on Information and Communication Technology Convergence (ICTC)
Year: 2019 | Conference Paper |
Cited by: Papers (7)
Cache side-channel attack extracts secret information by monitoring cache behavior of a victim. Normally, this attack targets a L3 cache which is shared between a spy and a victim. Hence, spy can learn about secret information without perception of the victim. To resist against this attack, many detection techniques have been proposed in the literature. However, those approaches have limitation si...Show More
Premises of evaluation of the filtration efficiency of an electrostatic precipitator by measuring of the electric charge
Malika Bengrit;Farid Miloua;Mohammed Miloudi;Amar Tilmatine;Lucian Dascalescu;Noureddine Zouzou
2015 IEEE Industry Applications Society Annual Meeting
Year: 2015 | Conference Paper |
Most particle counters of dust or smoke particles have a higher sensitivity than other detection systems and provide more information at least indicative of the filtering efficiency in the case of an electrostatic precipitator for example. This allows the intervention by the activation of automatic control systems for increasing the performance. But the major drawback of these detectors is their h...Show More
A fully-automated, liquid-moderated neutron spectrometer system
IEEE Nuclear Science Symposium & Medical Imaging Conference
Year: 2010 | Conference Paper |
A novel, water-based, neutron spectroscopy system has been designed, simulated, and tested at the National Research Council of Canada. The active part of the detection system is a small proportional counter sensitive to thermal neutrons. This is suspended along the symmetry axis of a large, rectangular water bath, and can be positioned remotely anywhere along this axis down to the bottom face. The...Show More
Constant-Time Synchronous Binary Counter With Minimal Clock Period
A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This brief proposes a new fast structure for synchronous...Show More
Investigating Black-Box Function Recognition Using Hardware Performance Counters
IEEE Transactions on Computers
Cited by: Papers (1)
This paper presents new methods and results for recognising black-box program functions using hardware performance counters (HPC), where an investigator can invoke and measure function calls. Important use cases include analysing compiled libraries, e.g., static and dynamic link libraries, and trusted execution environment (TEE) applications. We develop a generic approach to classify a comprehensi...Show More
LTL over Presburger constraints is the extension of LTL where the atomic formulae are quantifier-free Presburger formulae having as free variables the counters at different states of the model. This logic is known to admit undecidable satisfiability and model-checking problems. We study decidability and complexity issues for fragments of LTL with Presburger constraints obtained by restricting the ...Show More
A method for the measurement of the absolute value of w for X-rays in noble gases: results at 5.9 keV in xenon
A method is described that allows the measurement of the absolute value of the average energy to produce an ion pair, w, in noble gases for soft X-rays and its energy dependence. It uses a specially designed gas proportional scintillation counter working under electric fields below the ionization threshold. The spectrum of the radiation absorbed, and so the number of photons detected at each energ...Show More
A method for the measurement of the absolute value of the average energy to produce an ion pair in noble gases with X-rays
IEEE Conference on Nuclear Science Symposium and Medical Imaging
Year: 1992 | Conference Paper |
A method is described that allows the measurement of the absolute value of the average energy to produce an ion pair in noble gases for soft X-rays and its energy dependence. It uses a specially designed gas proportional scintillation counter working under electric fields below the ionization threshold. The spectrum of the radiation absorbed, and thus the number of photons detected at each energy ...Show More
Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
Young-Won Kim;Joo-Seong Kim;Jae-Hyuk Oh;Yoon-Suk Park;Jong-Woo Kim;Kwang-Il Park;Bai-Sun Kong;Young-Hyun Jun
A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bit...Show More
Using Hardware Performance Counters for Fault Localization
2010 Second International Conference on Advances in System Testing and Validation Lifecycle
Year: 2010 | Conference Paper |
Cited by: Papers (5)
In this work, we leverage hardware performance counters-collected data as abstraction mechanisms for program executions and use these abstractions to identify likely causes of failures. Our approach can be summarized as follows: Hardware counters-based data is collected from both successful and failed executions, the data collected from the successful executions is used to create normal behavior m...Show More
Can Hardware Performance Counters Detect Adversarial Inputs?
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
Deep learning has become an integral part of modern-day applications. Recent research has shown how inputs for a Neural Network can be perturbed to disrupt its detection accuracy and lead to fatal consequences. In this paper, we investigate whether hardware performance counters available in most modern microprocessors uncover adversarial inputs constructed using perturbations to the clean input im...Show More
Using Hardware Performance Counters to support infield GPU Testing
Juan-David Guerrero-Balaguera;Josie E. Rodriguez Condia;Matteo Sonza Reorda
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Year: 2021 | Conference Paper |
Graphics Processing Units (GPUs) have gained importance in several domains where a high computational effort is required (e.g., where Artificial Intelligence is used). At the same time, their adoption extended to domains (e.g., automotive, robotics, aerospace) where the effects of possible hardware faults can be extremely serious. Hence, it is crucial to identify methods allowing to quickly detect...Show More
Hardware performance counters based runtime anomaly detection using SVM
Muhamed Fauzi Bin Abbas;Sai Praveen Kadiyala;Alok Prakash;Thambipillai Srikanthan;Yan Lin Aung
The nature of ever evolving anomalies have become more sophisticated and complex in attacking the defense schemes, thereby leading to serious compromises. Existing software based techniques aim to protect a vulnerable software with another software which is also prone to compromise like obfuscation-based attacks. On the other hand, hardware performance counters offer a robust detection mechanism t...Show More
Hardware Performance Counters for Embedded Software Anomaly Detection
2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing, 4th Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech)
Year: 2018 | Conference Paper |
Cited by: Papers (11)
A recent trend in software security has utilized hardware performance counters as a security mechanism for integrity checks as well as malware detection. In this work we have developed two methods to check and validate the runtime integrity of a program to protect against malicious intrusions. The two methods developed utilize Hidden Markov Models and Long Short Term Memory neural networks trained...Show More
Development of C++ Program for Digital Synchronous Counter Design
Sandeep Kumar Sunori;
2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV)
Year: 2021 | Conference Paper |
Cited by: Papers (2)
The synchronous digital counter designing is conventionally done by following a systematic procedure. First of all, the minimum number of flip flops, required to implement the given counter, are determined depending on the modulus of given counter. Then, the present state-next state table is formulated, in which the excitation inputs for all of the flip-flops are clearly indicated for every presen...Show More
New Implementation of Frequency Generation Algorithm Using HDL
2009 Fourth International Conference on Computer Sciences and Convergence Information Technology
Year: 2009 | Conference Paper |
Frequency generation module is used in various information service equipments from low to high frequency application system. Many circuit systems have used one clock source to generate multiple frequencies. If oscillator of each frequency is divided by integer type division ratio, accurate frequency is generated. However in a case that a division ratio is a real number, it is difficult to achieve ...Show More
Performance of a Photomultiplier with a Porous Transmission Dynode
The root-mean-square deviation in number of secondary electrons from a normal secondary emitter increases with the square root of the secondary-emission ratio. The constant of proportionality is slightly greater than unity. The pulse-height resolution of a multiplier is therefore improved by the use of a high-gain first dynode. The secondary-emission ratio from a porous potassium chloride transmis...Show More
A Double-Edge Triggered Asynchronous Gray Counter for Use as a Coarse Counter in VCO ADCs
Johan Raman;Tobias Cromheecke;Simon Ooghe;Brendan Saux;Pieter Rombouts
This brief presents an asynchronous double-edge triggered Gray counter that can advantageously be used as coarse counter in a coarse-fine VCO ADC. We show that, in spite of using only a single counter and a single sampling register, it is possible to resolve the ambiguity in the coarse counter value caused by metastability and delay. We present simple decoding logic that performs both Gray-to-bina...Show More
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector
A new type of sampling error corrector for a time- to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least signif...Show More
PBCR: Parameter-based Backoff Counter Regulation in IEEE 802.15.6 CSMA/CA
2021 International Conference on COMmunication Systems & NETworkS (COMSNETS)
Year: 2021 | Conference Paper |
Cited by: Papers (10)
In this paper, we propose a Parameter-based Backoff Counter Regulation (PBCR) CSMA/CA mechanism to select backoff counter (BC) value based on various context parameters instead of selecting random backoff counter. We calculate BC value of sensor nodes based on various parameter indexes such as random backoff index (RBI), retransmission index (RI), buffer status index (BSI), packet generation rate ...Show More
Hot Block Ring Counter: A Low Power Synchronous Ring Counter
Mohammad Dastjerdi-Mottaghi;Anahita Naghilou;Masoud Daneshtalab;Ali Afzali-Kusha;Zainalabedin Navabi
2006 International Conference on Microelectronics
Year: 2006 | Conference Paper |
Cited by: Papers (2)
In this paper, we propose a new and low-power architecture for synchronous ring counters which can noticeably reduce the switching activity of the conventional ring counters. To achieve the goal we partition the ring counter into some blocks for each of which we use a special clock gator. The Hot block (the block in which the '1' exists) is the only block the flip-flops of which are clocked. The d...Show More
The minimizing prediction error on corporate financial distress forecasting model: An application of dynamic distress threshold value
2017 IEEE 8th International Conference on Awareness Science and Technology (iCAST)
Year: 2017 | Conference Paper |
Cited by: Papers (3)
In this study, we have adopted factors such as intellectual capital, financial ratios and corporate governance variables to construct a financial distress forecasting model by logistic regression. Furthermore, we employ the criteria of minimizing the sum of the two error probability in models I and II to determine the optimal threshold value, so as to increase the forecasting ability of a financia...Show More
Design and Development of a Chrono-Controller Using Synopsys Verdi Tool
2024 8th International Conference on Computational System and Information Technology for Sustainable Solutions (CSITSS)
Year: 2024 | Conference Paper |
The Chrono Controller is a sophisticated timer and counter system designed for precise timing and event management in control applications. This paper details the operation, verification, and results of a 24-bit Chrono Controller module, which supports advanced counter and compare functionalities. The Chrono Controller facilitates accurate scheduling and synchronization through its counter operati...Show More
This corrigendum to IEEE Std 802.1Q-2014 corrects technical and editorial errors identified by the IEEE 802.1 Working Groups maintenance activity.Show More
Standards Dictionary Terms
- 4-Way Handshake
- AES
- Authentication Server (AS)
- Authenticator
- Authenticator address (AA)
- CTR
- EAPOL-Key confirmation key (KCK)
- EAPOL-Key encryption key (KEK)
- FIPS
- GCM
- GF
- Group Key Handshake
- LBA
- Michael
- Supplicant
- Supplicant address (SPA)
- additional authentication data (AAD)
- associated data
- authentication and key management (AKM) suite
- authorized
- big endian
- cipher suite
- decapsulate
- decapsulation
- encapsulate
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