A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

A new type of sampling error corrector for a time- to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm² chip area.

I. Introduction

A time-to-digital converter (TDC) is widely used in many applications such as nuclear experiments for locating single-shot events, laser range finders, and space science instruments. Recently, it has been employed for phase measurement in all-digital phase-locked loops (ADPLLs) [1], [2]. ADPLLs are expected to replace traditional analog phase-locked loops (PLLs) because they do not require large on-chip capacitors and do not suffer from the capacitor leakage current problem, which can seriously degrade PLL jitter performance [3]. Furthermore, ADPLLs are more immune to external noises and process parameter, voltage, and temperature (PVT) variations since many ADPLL building blocks are realized with pure digital logic circuits. However, deterministic jitters are generated in ADPLLs from quantization noises due to digitization of analog phase/frequency signals. In order to minimize these, TDC resolution should be very fine. At the same time, the TDC input dynamic range should be large in order for the ADPLL to respond to large phase errors during the PLL pull-in process.