I. Introduction
In recent years, with the advent of the Internet of Things and the fifth-generation (5G) communications, low-cost and highly integrated CMOS millimeter-wave (mm-wave) circuits have become a research hotspot [1], [2], [3]. To increase the integration density of chips, the individual components on-chip should be placed as close as possible. Consequently, it leads to the adjacent sensitive components, especially inductors, which will suffer from performance degradation and further impact the whole circuit. The main reason is due to the electromagnetic coupling (EMC) and crosstalk [4]. An efficient way to solve this problem is employing guard rings to the periphery of the inductors. These guard rings greatly increase the isolation of the inductors [5], [6], [7]. However, using guard rings also affect the performance of the inductor itself, such as inductance (), quality factor (-factor), and self-resonance frequency (SRF) [8], [9]. Most studies in grounded guard rings (GGRs) are focused on discussing why GGR can increase isolation and reduce substrate noise [10], [11], [12]. According to the author’s knowledge, there are rarely discussed the effects of the guard ring on the performance of the inductors in great depth. Therefore, the motivation for this letter is to intuitively and deeply analyze the mechanism of the effects of GGR on the performance of inductors.