System-Level ESD-Induced Voltage Fluctuation to the Power of Integrated Circuits on System Board

Based on the voltage and current waveforms, the mechanism of the system-level electrostatic-discharge (ESD) induced the voltage fluctuation to the power of integrated circuits (ICs) on system board is studied. When a contact discharge ESD test is performed at a connector pin, which is terminated with an I/O pin of an IC, not all the current from the system-level ESD may flow through the IC to the ground of the system board. So, the remaining currents can only flow through the power line of the ICs and the connection wire into the power supply to the ground. The power supply has the feedback and pulsewidth modulation circuits to regulate its output voltage. Therefore, the output current of the power supply will interact with the remnant current from the ICs on system board, resulting in the current flowing through the connection wire in the microelectronics system back and forth. Hence, the power of system board will be pulled up and down by the connection wire based on L·(dI/dt), since it acts as an inductor during the alternating current. With the voltage swinging up and down, the p-n junctions in the power domain seems to be driven into the avalanche breakdown or forwarded to generate a lot of electrons and holes inside the ICs, leading to the latch-up event at the low latch-up immunity region.

I. Introduction

System-level electrostatic-discharge (ESD) is intended to emulate the real world ESD event on an electrical system of end-user such as charged human, charged human with a metal tool, charge cable, and charged metal objects [1]. The ISO 10605 and IEC 61000-4-2 are defined as a standard to illustrate a charged human holding a metal object to touch one point of the electrical system and the test modes (air-discharge and contact-discharge) in the automotive and nonautomotive system applications, respectively [2], [3]. Now, it is commonly used to evaluate the level of system-level ESD for key board, microcontroller [4], finger printer [5], [6], display panel [7], [8], automotive [9], [10], and touch panel [11]. The level of system-level ESD is defined as the maximum voltage that does not interrupt the electrical system. If the zapping voltage of system-level ESD is beyond the level of a system board, it might induce the latch-up to lead the soft error to upset or frozen the states in the system [7], [11], [12], [13], [14], [15], [16], resulting in the system shutdown and catastrophic damage [5], [6]. The root cause was identified as the system-level ESD induced the voltage fluctuation of the power of system board regardless of air-discharge or contact-discharge test mode [2], [3], [4], [7]. It gives rise to voltage overshoot and undershoot to the power of system board several times. So, the bipolar trigger transient latch-up is proposed to replicate this phenomenon instead of unipolar trigger latch to reproduce same failure site as on-board failure [17], [18], [19]. Now, the device used to discharge the system-level ESD is the diode regardless of the off-chip ESD component (transient voltage suppressor) or on-chip ESD component (parasitic diode of output driver or embedded diode) [9], [10]. However, the diode only conducts the current of positive system-level ESD to the V_DD of a chip. Then, this current still needs to sink by the circuits connected to the V_DD to the ground regardless of the chip or power supply. Hence, the current will flow back and forth between the circuit of chip and power supply through the connection wire (inductor), resulting in the voltage fluctuation. Although this effect had been observed in earlier literature [4], the detail mechanism is not clearly discussed. In this article, how the current of the system-level ESD interacts with the output current of power supply is investigated and discussed in detail.