Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology

Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts to limit their series resistance contribution to ten percent of the device channel resistance. This requires not only extremely low junction sheet resistance values but also super abrupt doping profiles and contact resistivities that can not be obtained with the existing self-aligned silicide technology. In this paper, we present an overview of the SiGe junction technology designed to meet the demands of the future technology nodes down to 30 nm. The technology is based upon selective deposition of boron or phosphorus doped SiGe in source/drain areas isotropically etched to the desired junction depth. The technology is limited to temperatures below 800/spl deg/C. Hence; it is also compatible with future high-/spl kappa/ gate stacks, which can not withstand higher temperatures. The results indicate that the technology offers great promise in meeting the demands of the end-of-the-roadmap devices.

Introduction

Future CMOS technology nodes will require extension and contacting junctions as shallow as 8 nrn⁻¹. The junctions must also fulfill several criteria to limit the series resistance contribution of each junction to five percent of the channel resistance. These criteria include low resistivity to scale the sheet resistance of the extension junction under the sidewall spacer, abrupt j unction doping profile to minimize junction spreading resistance and finally, contact resistivity near 10⁻⁸ ohm-ern”, Furthermore, compared to Si0₂, the thermal stability offuture high-K gate dielectric materials are expected to be considerably less, which introduces low temperature processing as a new challenge to source/drain formation. The high-K research community is predicting a temperature limit around 80°C.