Smooth Pulse Number Transition Strategy Considering Time Delay in Synchronized SVPWM

In high power motor drive systems, synchronized space vector pulsewidth modulation (synchronized SVPWM) is widely used to guarantee stable control performance. Synchronized SVPWM has a characteristic that the switching frequency varies abruptly when the pulse number transitions. This article proposes a pulse number transition point at which the phase difference is minimized to remove the phase difference of the sampling point that appears during synchronized SVPWM control. In addition, for a smooth pulse number transition of synchronized SVPWM, a compensation method for the magnitude and phase error of the inverter output voltage due to the time delay and a method of removing the existing phase difference without using a phase-locked loop are proposed in consideration of the characteristic of changing switching frequency. The validity and the implementation of the proposed method are verified by experimental results using a high-power inverter driving 332 kW interior permanent magnet synchronous motor (IPMSM).

I. Introduction

Controlling a voltage source inverter (VSI) using a high switching frequency in a high power motor drive system increases the ratio of the switching loss to the total power conversion loss due to the frequent switching operation of the power semiconductor. Therefore, the switching frequency of VSI is limited from a few hundred Hz to 1 kHz to reduce the switching loss, the temperature rise, and as a result, in the volume of the cooling system [1], [2], [3], [4], [5]. However, when conventional asynchronized pulsewidth modulation (PWM) is performed using a low switching frequency, harmonics, and subharmonics are generated [6], and these harmonics cause additional loss and oscillation. In addition, an output voltage imbalance occurs due to the asynchronization between the inverter output fundamental wave and the carrier wave [7]. In the high-speed region of the motor, the frequency of the inverter fundamental wave increases. Therefore, the number of switching pulses of the inverter decreases during one period of the fundamental wave, which increases the output voltage imbalance. To eliminate the disadvantages of asynchronized PWM with a low switching frequency, synchronized PWM is used.