I. Introduction
Cryogenic CMOS are now widely considered an appealing method of interfacing with sensors and quantum information systems that operate in sub-Kelvin cryogenic environments, offering a number of advantages over conventional room temperature electronics chains [1] . In particular, cryogenic electronics offer the opportunity for more precise readout and control of devices in the cryogenic environment by virtue of proximity, improving latency and reducing the impact of noise pickup in the cabling. They also allow for cold multiplexing, significantly reducing the required amount of cryogenic cabling, which could otherwise impose prohibitive thermal loads on a cryogenic setup as channel numbers are scaled up.