Scheduling Active and Accelerated Recovery to Combat Aging in Integrated Circuits

As semiconductor chips are widely adopted in mission- or safety-critical application domains, and as the scale of these chips increases dramatically with heterogeneous integration, there is a growing interest in extending the silicon lifetime. This is especially true in scenarios like automotive, data center or medical devices. Even in consumer electronics like cell phones, the cost of the design drives up the necessity of designing highly reliable chips that last longer. Chip aging, a device-level degradation mechanism, has been a major threat to silicon lifetime. It happens to all major parts of a computing system, such as computation/memory, interconnects, and storage. This paper demonstrates this with the most critical and dominant aging phenomena, BTI, EM, and flash wearout. Although each unique aging phenomenon is characterized in its own way, damages are all caused when the design is subjected to some forms of electric stress, either voltage or current. In this paper, we look into all these major aging effects from a global view, in which we analyze the commonalities and propose to schedule the active and accelerated periods proactively to fundamentally “attack the cause” instead of “attack the symptom We present experimental results and implementation details, followed by a global scheduler that aims to conduct “scheduled recovery” in an all-in-one fashion.