Efficient Load Balance Algorithm for Network-on-Chip Mapping

With the significant improvement of System-on-Chip (SoC), Network-on-Chip (NoC) is proposed to solve its communication problem. Considering that Processor Elements (PEs) are integrated into NoC, the load balance of NoC should be investigated carefully as it influences the performance of NoC mapping to a large extent. In this context, an effective mapping strategy becomes a new challenge for NoC. Therefore, this paper introduces the efficient load balance algorithm (ELB) targeting at NoC mapping, which fully considers the relationship among tasks and the utilization of resources. The simulation results show that, compared to the classic Genetic Algorithm (GA), the performance of ELB is relatively superior, especially power consumption and load balance. In addition, the processing time cost by ELB is three orders of magnitude less than GA, which reveals the high efficiency of ELB.

I. Introduction

Due to the advancement of semiconductor process technology and integrated circuits, the integration of SoC is becoming more complicated, and it is urgent to solve the problems of high busload and degraded network communication performance [1]. To this end, as a new technology for interconnection communication, NoC has the potential ability to meet the communication needs of PEs on-chip, which overcomes the defects of traditional structure and realizes high performance on data communication between PEs by using the ideal of Internet [2].