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A Novel Dynamic Logic Circuit with Low Leakage Power and Propagation Delay | IEEE Conference Publication | IEEE Xplore

A Novel Dynamic Logic Circuit with Low Leakage Power and Propagation Delay


Abstract:

Dynamic logic circuits are used in highly efficient VLSI devices. Problem arises when the dynamic logic circuit’s performance falls due to its high propagation delay and ...Show More

Abstract:

Dynamic logic circuits are used in highly efficient VLSI devices. Problem arises when the dynamic logic circuit’s performance falls due to its high propagation delay and high leakage power. A novel dynamic logic model with low leakage power and propagation delay in contrast to previous models, is developed by modifying stacking effect circuitry. The LTSpice tool is used to illustrate the robustness of the proposed model utilizing 45nm PTM technology for the OR logic gate functionality.
Date of Conference: 27-29 May 2022
Date Added to IEEE Xplore: 15 July 2022
ISBN Information:
Conference Location: Belgaum, India

I. Introduction

In the industry of electronics, the dynamic logic circuit has gained popularity. The static logic circuit was used once upon a time. However, a huge number of transistors are required in static logic circuits, resulting in a large overhead area and significant power dissipation [1]. In comparison to static logic circuits, dynamic logic circuits require almost half the number of transistors. As a result, it is being phased out in favor of dynamic logic, which outperforms static logic [2].

References

References is not available for this document.