A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS

This paper presents a 1.5-GS/s 6-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) using speculative capacitive DAC (CDAC) switching control technique. The proposed SAR ADC achieves a high sampling rate by eliminating additional delays in typical loop-unrolled SAR ADCs related to settling time constraints in their CDACs. Specifically, the CDACs are duplicated and controlled in speculative ways so that the CDAC outputs passage to their next values before completing the regeneration operation of comparators, thereby improving timing constraints for successive approximations. The switching power overhead from the CDAC speculation is mitigated by introducing an energy-efficient CDAC control technique that produces desired voltage transients with minimal power overheads. The prototype of the proposed SAR ADC is fabricated in a 28-nm CMOS technology and occupies an active area of 0.0038-mm². The design consumes 5.8 mW from a 1.2-V supply. The ADC achieves 1.5-GS/s sampling frequency with a 31-dB SNDR at a low input frequency and a 28.6 dB at the Nyquist frequency without applying any offset calibration techniques, achieving the highest sampling frequency among the 6-bit single-channel loop-unrolled SAR ADCs reported.

I. Introduction

As the bandwidth requirements on high-speed wireline and wireless communication systems are continuously increasing, there are significant demands on high sampling-rate, medium-resolution, and power-efficient ADCs. Flash ADCs have been widely used for implementing high sampling-rate ADCs for decades [1]–[3], however, they suffer from their exponentially increasing number of comparators for achieving high resolutions, which in turn increases power consumption and hardware complexity significantly. This problem can be mitigated by using SAR ADCs, as they require a smaller number of comparators due to their sequential approximation process. The SAR ADCs achieve high energy efficiencies as well, because they utilize digital circuits for most of their building blocks, which do not consume static power and are feasible to transistor scaling. The timing constraints associated with the successive approximation operation are readily fulfilled by interleaving multiple SAR ADC slices in time domain, which enables >10-GS/s conversion speeds. However, the maximum number of interleaved slices is limited by power consumption and hardware complexity overheads related to the time interleaving. Hence, the sampling rate of sub-ADC slices should be maximized to minimize the interleaving ratio, thereby avoiding collateral design issues related to the excessive time interleaving of SAR ADCs.