Variability-Aware Approximate Circuit Synthesis via Genetic Optimization

One of the major barriers that CMOS devices face at nanometer scale is increasing parameter variation due to manufacturing imperfections. Process variations severely inhibit the reliable operation of circuits, as the operational frequency at the nominal process corner is insufficient to suppress timing violations across the entire variability spectrum. To avoid variability-induced timing errors, previous efforts impose pessimistic and performance-degrading timing guardbands atop the operating frequency. In this work, we employ approximate computing principles and propose a circuit-agnostic automated framework for generating variability-aware approximate circuits that eliminate process-induced timing guardbands. Variability effects are accurately portrayed with the creation of variation-aware standard cell libraries, fully compatible with standard EDA tools. The underlying transistors are fully calibrated against industrial measurements from Intel 14nm FinFET in which both electrical characteristics of transistors and variability effects are accurately captured. In this work, we explore the design space of approximate variability-aware designs to automatically generate circuits of reduced variability and increased performance without the need for timing guardbands. Experimental results show that by introducing negligible functional error of merely $\boldsymbol {5.3 \times 10^{-3}}$ , our variability-aware approximate circuits can be reliably operated under process variations without sacrificing the application performance.

I. Introduction

Technology scaling has brought significant challenges to circuit designers due to the intrinsic physical limitations of silicon devices [1]. One of the major barriers that CMOS devices face at nanometer scale is increasing process parameter variations. Process imperfections, such as metal work-function, random dopant fluctuations and line-edge roughness cause devices to exhibit large variability in their electrical parameters, particularly in the threshold voltage , as well as in other device parameters (e.g., channel length, gate width, oxide thickness) [2] and circuit wiring. Thus, the operating frequency becomes unsustainable under the effect of process variations, leading to unpredictable timing violations [3]. For the examined circuits in this work, Fig. 1 presents the worst-case error due to timing violations (details on the experimental setup can be found in Section VI). Both the error magnitude and the peak differentiation among circuits (one order of magnitude) showcase their unpredictability and catastrophic nature. Hence, parametric yield of a circuit (i.e., probability to meet the desired performance specification) is expected to suffer considerably under process variations and thus, reliable operation cannot be guaranteed. Fig. 1.

Worst-case error evaluation obtained from a 1000-point monte-carlo variability analysis for several arithmetic circuits, image processing benchmarks, and machine learning classifiers (see Section VI). The normalized mean error distance (NMED) error metric is used (see Section V-B.1).