Bayesian Photonic Accelerators for Energy Efficient and Noise Robust Neural Processing

Artificial neural networks are efficient computing platforms inspired by the brain. Such platforms can tackle a vast area of real-life tasks ranging from image processing to language translation. Silicon photonic integrated chips (PICs), by employing coherent interactions in Mach-Zehnder interferometers, are promising accelerators offering record low power consumption and ultra-fast matrix multiplication. Such photonic accelerators, however, suffer from phase uncertainty due to fabrication errors and crosstalk effects that inhibit the development of high-density implementations. In this work, we present a Bayesian learning framework for such photonic accelerators. In addition to the conventional log-likelihood optimization path, two novel training schemes are derived, namely a regularized version and a fully Bayesian learning scheme. They are applied on a photonic neural network with 512 phase shifters targeting the MNIST dataset. The new schemes, when combined with a pre-characterization stage that provides the passive offsets, are able to dramatically decrease the operational power of the PIC beyond 70%, with just a slight loss in classification accuracy. The full Bayesian scheme, apart from this energy reduction, returns information with respect to the sensitivity of the phase shifters. This information is used to de-activate 31% of the phase actuators and, thus, significantly simplify the driving system.

I. Introduction

Artificial neural networks (ANN) include a wide bio-inspired class of algorithms that is capable of learning and analyzing vast amount of data without being grounded on explicit instructions [1]. ANNs have allowed the development of a large area of novel information processing schemes that range from machine vision to language translation and audio processing [1]–[4]. The first ANNs have been implemented in traditional Von Neumann devices. However, as the number of available data is increased along with the need for fast processing, such computational paradigms suffer from an inherent problem, which is the separation between the central processing unit (CPU) and the memory unit [5]. To this end, a great amount of research nowadays focuses on new hardware architectures that break free from these limitations. Graphical Processing Units (GPUs) [6], application-specific integrated circuits (ASICs) [7], neuromorphic chips such as IBM's True North [8] and Intel's Loihi [9], have demonstrated considerable improvements in energy efficiency and processing speed.