I. Introduction
With the demand of large storage capacity, the 2D planar flash memory architecture has been replaced by the 3D flash memory architecture, which is widely adopted in modern devices [10]. However, 3D flash memory exhibits a significant degree of process variation [22], [28], which affects the characteristics of different flash blocks. Specifically, blocks in the same flash chips could have different read/write latency and raw bit error rates (RBER). This brings challenges to designing a reliable SSD.