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Memristor based full subtractor | IEEE Conference Publication | IEEE Xplore

Memristor based full subtractor


Abstract:

Extending the use of memristor technology beyond memory to computing has recently received a lot of attention. Memristor-based logic design is a new approach that aims to...Show More

Abstract:

Extending the use of memristor technology beyond memory to computing has recently received a lot of attention. Memristor-based logic design is a new approach that aims to make computing systems more efficient. In this paper, a one-bit full subtractor is implemented using MAND, MOR, and XOR gates. The proposed circuit's simulation results, which include all of the above gates, have been published. In comparison to a typical circuit, the proposed circuit has less area, delay but has larger power dissipation when compared with CNTFET due to high memristance. The circuit was simulated in cadence virtuoso with the VTEAM memristor model.
Date of Conference: 10-11 March 2022
Date Added to IEEE Xplore: 12 May 2022
ISBN Information:
Conference Location: Chennai, India

I. Introduction

Memristor is a fourth fundamental 2-terminal passive non-linear circuit element found by Leon Chua [1] in 1971, which works on the charge-magnetic flux relationship. The relation between four fundamental elements is depicted in fig. 1.

Fundamental circuit variable relationships

References

References is not available for this document.